JasmineDoc.tioga
Created by Neil Gunther, January 27, 1986 2:56:07 pm PST
Last Edited by: Neil Gunther October 8, 1986 11:01:12 am PDT
Purpose
Enumerate the rectangles belonging to a Core wire, and transform them into the equivalent lumped LRC network. Use Thyme to analyze the degree of voltage swing, taking into account diode thresholds, block circuit transitions, ..., etc..
Manual Static Analysis Procedure
To compute voltage drops in the power bus due to peak current flow the power bus is modeled as a tree that is rooted at the pad and branches at each major block shown on the floor plan. Each node in the tree represents a junction of lower level power buses. Each link in the tree represents the metal required to join one junction to the next. The voltage drop in each link of the tree is the sum of the currents required by each of the leaf blocks beneath the link, multiplied by the resistance of the link.
User Interface
A particular power bus analysis is initiated by selecting the appropriate wire in the layout. The user should be able to specify which subcircuits to include or ignore in the analysis & also provide predetermined parameters for the lumped element network. The results of the analysis should be fed back to the user with reference to the original layout for circuit debugging purposes.
Rectangle Preprocessing (April 24, 1986)
All the rectangles on a Core wire need to be enumerated so that compound areas i.e. rectangles composed of several abutting and overlapping rectangles of arbitrary size, can be detected and treated as special cases before the transformation to the equivalent circuit. Moreover, the fissioning algorithm described below depends on a knowledge of the orientation of the length and width dimensions of the intersecting rectangles. Since the code is readily available, it is proposed to preprocess the Core wire into a Canonical form using a Corner Stitching data structure.