Test74LS163.mesa
Copyright © 1985 by Xerox Corporation. All rights reserved.
Last Edited by: Gasbarro October 15, 1986 11:31:30 am PDT
DIRECTORY
Core, CoreCreate, ICTest, Ports, Rope, TestCable;
Test74LS163: CEDAR PROGRAM
IMPORTS CoreCreate, ICTest, Ports, TestCable
= BEGIN
Nibble: TYPE = [0..16);
nClear: NAT = 0;
Clock: NAT = 1;
DataIn: NAT = 2; --4 bits
EnableP: NAT = 3;
Gnd: NAT = 4;
nLoad: NAT = 5;
EnableT: NAT = 6;
DataOut: NAT = 7; --4 bits
RippleCarryOut: NAT = 8;
Vcc: NAT = 9;
width: NAT = 4;
thisTest: Rope.ROPE = "74LS163 Tester";
Init: PROC = {
R: PROC [a: ICTest.Assignments] = {
assignments←CONS[a,assignments];
};
groups: LIST OF ICTest.Group ← NIL;
assignments: LIST OF ICTest.Assignments ← NIL;
ct: Core.CellType ← CoreCreate.Cell[
name: "74LS163",
public: CoreCreate.WireList[LIST[
"nClear", "Clock", CoreCreate.Seq["DataIn", width], "EnableP", "Gnd", "nLoad", "EnableT", CoreCreate.Seq["DataOut", width], "RippleCarryOut", "Vcc"]],
onlyInternal: NIL,
instances: NIL
];
groups ← LIST[
[number: 1, name: "DUTInputs", directionality: force, format: DNRZ, delay: 10],
[number: 2, name: "DUTOutputs", directionality: acquire, sample: 40],
[number: 3, name: "Clocks", directionality: force, format: RZ, delay: 0, width: 20]
];
assignments ← NIL;
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Signal Name p d e r e l r r n
R[["Gnd", 0,0,R,AB, A,0,001,001, 8]];
R[["Vdd", 0,0,R,AB, A,0,001,001, 16]];
R[["nClear", 1,0,R,AB, A,0,001,001, 1]];
R[["DataIn[0]", 1,0,R,AB, A,1,001,001, 6]]; --MSB
R[["DataIn[1]", 1,0,R,AB, A,2,001,001, 5]];
R[["DataIn[2]", 1,0,R,AB, A,3,001,001, 4]];
R[["DataIn[3]", 1,0,R,AB, A,4,001,001, 3]]; --LSB
R[["EnableP", 1,0,R,AB, A,5,001,001, 7]];
R[["nLoad", 1,0,R,AB, A,6,001,001, 9]];
R[["EnableT", 1,0,R,AB, A,7,001,001, 10]];
R[["RippleCarryOut", 2,0,R,CD, A,0,001,001, 15]];
R[["DataOut[0]", 2,0,R,CD, A,1,001,001, 14]]; --MSB
R[["DataOut[1]", 2,0,R,CD, A,2,001,001, 13]];
R[["DataOut[2]", 2,0,R,CD, A,3,001,001, 12]];
R[["DataOut[3]", 2,0,R,CD, A,4,001,001, 11]]; --LSB
R[["Clock", 3,0,R,AB,AT,0,001,001, 2]];
[] ← Ports.InitPort[ct.public[DataIn], c];
[] ← Ports.InitPort[ct.public[DataOut], c];
Ports.InitTesterDrive[ct.public[nClear], force];
Ports.InitTesterDrive[ct.public[Clock], force];
Ports.InitTesterDrive[ct.public[DataIn], force];
Ports.InitTesterDrive[ct.public[EnableP], force];
Ports.InitTesterDrive[ct.public[nLoad], force];
Ports.InitTesterDrive[ct.public[EnableT], force];
Ports.InitTesterDrive[ct.public[DataOut], none];
Ports.InitTesterDrive[ct.public[RippleCarryOut], none];
TestCable.Init[groups, assignments, "Clock"];
ICTest.MakeStandardViewer[testName: thisTest, cellType: ct, clockAName: "Clock", groups: groups, assignments: assignments, period: 60];
};
DoTest: ICTest.TestProc = {
count: Nibble;
temp: Nibble;
Cycle: PROC = {
t: Nibble ← p[DataOut].c;
p[DataOut].c ← temp;
p[RippleCarryOut].b ← temp=15;
temp ← t;
Eval[];
};
InitState: PROC ~ {
p[nClear].b ← FALSE;
p[Clock].b ← TRUE; --fire clock pulse every cycle
p[DataIn].c ← 0;
p[EnableP].b ← TRUE;
p[nLoad].b ← TRUE;
p[EnableT].b ← TRUE;
p[DataOut].d ← none;
p[RippleCarryOut].d ← none;
p[DataOut].c ← 0;
count ← 0;
Cycle[];
p[DataOut].d ← expect;
p[RippleCarryOut].d ← expect;
};
Clear: PROC ~ {
p[nClear].b ← FALSE;
p[DataOut].c ← 0;
count ← 0;
p[RippleCarryOut].b ← FALSE;
Cycle[];
p[nClear].b ← TRUE;
};
Load: PROC [value: Nibble] ~ {
p[nLoad].b ← FALSE;
p[DataIn].c ← value;
p[DataOut].c ← value;
count ← value;
p[RippleCarryOut].b ← count=15;
Cycle[];
p[nLoad].b ← TRUE;
};
IncCount: PROC ~ {
count ← IF count=15 THEN 0 ELSE count+1;
};
Count: PROC ~ {
IncCount[];
p[DataOut].c ← count;
p[RippleCarryOut].b ← count=15;
Cycle[];
};
InitState[];
Clear[];
THROUGH [0..16) DO
Count[];
ENDLOOP;
Load[8];
Load[4];
Load[2];
Load[1];
Load[0];
};
Init[];
ICTest.RegisterTestProc[thisTest, "DoTest", DoTest];
ICTest.RegisterTestProc[thisTest, "TestCable", TestCable.TestCable];
END.