DIRECTORY Core, CoreCreate, ICTest, Ports, Rope, TestCable; Test74LS163: CEDAR PROGRAM IMPORTS CoreCreate, ICTest, Ports, TestCable = BEGIN Nibble: TYPE = [0..16); nClear: NAT = 0; Clock: NAT = 1; DataIn: NAT = 2; --4 bits EnableP: NAT = 3; Gnd: NAT = 4; nLoad: NAT = 5; EnableT: NAT = 6; DataOut: NAT = 7; --4 bits RippleCarryOut: NAT = 8; Vcc: NAT = 9; width: NAT = 4; thisTest: Rope.ROPE = "74LS163 Tester"; groups: ICTest.Groups _ NIL; oldPeriod: ICTest.Period; Init: PROC = { R: PROC [a: ICTest.Assignment] = { assignments_CONS[a,assignments]; }; initialPeriod: ICTest.Period=60; assignments: ICTest.Assignments _ NIL; ct: Core.CellType _ CoreCreate.Cell[ name: "74LS163", public: CoreCreate.WireList[LIST[ "nClear", "Clock", CoreCreate.Seq["DataIn", width], "EnableP", "Gnd", "nLoad", "EnableT", CoreCreate.Seq["DataOut", width], "RippleCarryOut", "Vcc"]], onlyInternal: NIL, instances: NIL ]; oldPeriod _ initialPeriod; groups _ LIST[ [number: 1, name: "DUTInputs", directionality: force, format: DNRZ, delay: 10], [number: 2, name: "DUTOutputs", directionality: acquire, sample: 40], [number: 3, name: "Clocks", directionality: force, format: RZ, delay: 0, width: 20] ]; assignments _ NIL; R[["Gnd", 0, 0,R,AB, A,0,001,001, 8]]; R[["Vdd", 0, 0,R,AB, A,0,001,001, 16]]; R[["nClear", 1, 0,R,AB, A,0, 25,207, 1]]; R[["EnableP", 1, 0,R,AB, A,5, 30,201, 7]]; R[["nLoad", 1, 0,R,AB, A,6, 31,199, 9]]; R[["EnableT", 1, 0,R,AB, A,7, 32,198, 10]]; R[["DataIn[0]", 1, 0,R,AB, A,1, 26,202, 6]]; --MSB R[["DataIn[1]", 1, 0,R,AB, A,2, 27,203, 5]]; R[["DataIn[2]", 1, 0,R,AB, A,3, 28,204, 4]]; R[["DataIn[3]", 1, 0,R,AB, A,4, 29,205, 3]]; --LSB R[["RippleCarryOut", 2, 0,R,CD, A,0, 41,195, 15]]; R[["DataOut[0]", 2, 0,R,CD, A,1, 42,180, 14]]; --MSB R[["DataOut[1]", 2, 0,R,CD, A,2, 43,196, 13]]; R[["DataOut[2]", 2, 0,R,CD, A,3, 44,197, 12]]; R[["DataOut[3]", 2, 0,R,CD, A,4, 45,213, 11]]; --LSB R[["Clock", 3, 0,R,AB,AT,0,126,206, 2]]; [] _ Ports.InitPort[ct.public[DataIn], c]; [] _ Ports.InitPort[ct.public[DataOut], c]; Ports.InitTesterDrive[ct.public[nClear], force]; Ports.InitTesterDrive[ct.public[Clock], force]; Ports.InitTesterDrive[ct.public[DataIn], force]; Ports.InitTesterDrive[ct.public[EnableP], force]; Ports.InitTesterDrive[ct.public[nLoad], force]; Ports.InitTesterDrive[ct.public[EnableT], force]; Ports.InitTesterDrive[ct.public[DataOut], none]; Ports.InitTesterDrive[ct.public[RippleCarryOut], none]; TestCable.Init[groups, assignments, "Clock"]; ICTest.MakeStandardViewer[testName: thisTest, cellType: ct, clockAName: "Clock", groups: groups, assignments: assignments, period: initialPeriod]; }; PeriodChange: ICTest.PeriodChangeProc ~ { FOR g: ICTest.Groups _ groups, g.rest WHILE g#NIL DO g.first.delay _ (g.first.delay*period)/oldPeriod; g.first.width _ (g.first.width*period)/oldPeriod; g.first.sample _ (g.first.sample*period)/oldPeriod; ENDLOOP; RETURN[groups]; }; DoTest: ICTest.TestProc = { count: Nibble; temp: Nibble; Cycle: PROC = { t: Nibble _ p[DataOut].c; p[DataOut].c _ temp; p[RippleCarryOut].b _ temp=15; temp _ t; Eval[]; }; InitState: PROC ~ { p[nClear].b _ FALSE; p[Clock].b _ TRUE; --fire clock pulse every cycle p[DataIn].c _ 0; p[EnableP].b _ TRUE; p[nLoad].b _ TRUE; p[EnableT].b _ TRUE; p[DataOut].d _ none; p[RippleCarryOut].d _ none; p[DataOut].c _ 0; count _ 0; Cycle[]; p[DataOut].d _ expect; p[RippleCarryOut].d _ expect; }; Clear: PROC ~ { p[nClear].b _ FALSE; p[DataOut].c _ 0; count _ 0; p[RippleCarryOut].b _ FALSE; Cycle[]; p[nClear].b _ TRUE; }; Load: PROC [value: Nibble] ~ { p[nLoad].b _ FALSE; p[DataIn].c _ value; p[DataOut].c _ value; count _ value; p[RippleCarryOut].b _ count=15; Cycle[]; p[nLoad].b _ TRUE; }; IncCount: PROC ~ { count _ IF count=15 THEN 0 ELSE count+1; }; Count: PROC ~ { IncCount[]; p[DataOut].c _ count; p[RippleCarryOut].b _ count=15; Cycle[]; }; InitState[]; Clear[]; THROUGH [0..16) DO Count[]; ENDLOOP; Load[8]; Load[4]; Load[2]; Load[1]; Load[0]; }; Init[]; ICTest.RegisterTestProc[thisTest, "DoTest", DoTest]; ICTest.RegisterTestProc[thisTest, "TestCable", TestCable.TestCable]; ICTest.RegisterPeriodChangeProc[thisTest, PeriodChange]; END. –Test74LS163.mesa Copyright c 1985 by Xerox Corporation. All rights reserved. Last Edited by: Gasbarro February 14, 1987 11:26:09 am PST L o a T d e s B t D o e U a P r T r o C D d d h H H U G B a e e T r o S P B n a a o a i a y n d d P u r d i t e e e i Signal Name p d e r e l r r n --PROC [period: Period] RETURNS [newGroups: Groups]-- Κ£˜™Icodešœ Οmœ1™žœ ˜OKšœE˜EKšœ;žœ˜SKšœ˜—Kšœžœ˜K˜K˜JšΟf ™ Jš’+™+Jš’+™+Jš’+™+Jš’+™+Jš’/™/Jš’/™/Jš’/™/Jš’3™3Jš’3™3Jš’3™3Jš’2™2Jš’3™3Jš’3™3JšΠfz7™7Jš’7˜7Jš’7˜7J˜Jš’7˜7Jš’7˜7Jš’7˜7Jš’7˜7J˜Jš’=˜=Jš’7˜7Jš’7˜7Jš’=˜=J˜Jš’7˜7J˜Jš’=˜=Jš’7˜7Jš’7˜7Jš’=˜=J˜Jš’7˜7J˜J˜J˜Kšœ*˜*Kšœ+˜+K˜Kšœ0˜0Kšœ/˜/Kšœ0˜0Kšœ1˜1Kšœ/˜/Kšœ1˜1Kšœ0˜0Kšœ7˜7Kšœ-˜-Kšœ’˜’K˜K˜—š‘ œ˜)Kšœ5™5šžœ#žœžœž˜4Kšœ1˜1Kšœ1˜1Kšœ3˜3Kšžœ˜—Kšžœ ˜K˜K˜—š‘œ˜Kšœ˜K˜ K˜š‘œžœ˜Kšœ˜Kšœ˜Kšœ˜Kšœ ˜ Kšœ˜Kšœ˜—K˜š‘ œžœ˜Kšœžœ˜Kšœ žœ ˜1Kšœ˜Kšœžœ˜Kšœ žœ˜Kšœžœ˜Kšœ˜Kšœ˜Kšœ˜K˜ Kšœ˜Kšœ˜Kšœ˜K˜—K˜š‘œžœ˜Kšœžœ˜Kšœ˜K˜ Kšœžœ˜Kšœ˜Kšœžœ˜K˜K˜—š‘œžœ˜Kšœ žœ˜Kšœ˜Kšœ˜K˜Kšœ˜Kšœ˜Kšœ žœ˜K˜K˜—š‘œžœ˜Kšœžœ žœžœ ˜(K˜K˜—š‘œžœ˜Kšœ ˜ Kšœ˜Kšœ˜Kšœ˜K˜K˜—K˜ K˜šžœ ž˜K˜Kšžœ˜—K˜K˜K˜K˜K˜Kšœ˜K˜—K˜K˜Kšœ4˜4KšœD˜DKšœ8˜8Kšžœ˜—…—ό5