TestCableImpl.mesa
Copyright © 1986 by Xerox Corporation. All rights reserved.
Last Edited by: Gasbarro October 3, 1986 12:21:02 pm PDT
Don Curry January 31, 1987 2:54:20 pm PST
DIRECTORY
Basics, Commander, Core, CoreOps, IO, ICTest, Ports, Rope, TerminalIO, TestCable;
TestCableImpl: CEDAR PROGRAM
IMPORTS Basics, IO, CoreOps, Ports, Rope, TerminalIO
EXPORTS TestCable
= BEGIN
groupList: ICTest.Groups;
assignmentList: ICTest.Assignments;
clockAName: Core.ROPE;
clockBName: Core.ROPE;
Init:
PUBLIC
PROC [groups: ICTest.Groups, assignments: ICTest.Assignments, clockA, clockB: ICTest.
ROPE ←
NIL] ~ {
groupList ← groups;
assignmentList ← assignments;
clockAName ← clockA;
clockBName ← clockB;
};
TestCable:
PUBLIC ICTest.TestProc = {
InitDrive:
PROC [wire: Core.Wire, port: Ports.Port]
RETURNS [subElements:
BOOL ←
TRUE, quit:
BOOL ←
FALSE]
--Ports.EachPortPairProc-- = {
IF port#NIL THEN port.d ← force;
};
EachPair:
PROC [wire: Core.Wire, port: Ports.Port]
RETURNS [subElements:
BOOL ←
TRUE, quit:
BOOL ←
FALSE]
--Ports.EachPortPairProc-- = {
Cycle:
PROC = {
Eval[];
};
IF CoreOps.IsFullWireName[cellType.public, wire, a.name]
AND a.group#0
THEN {
IF port=
NIL
THEN
SELECT rootPort.levelType
FROM
ls => {};
bs => {};
c => {rootPort.c ← Basics.
BITSHIFT[08000h, -rootPort.fieldStart-count]; Cycle[];
rootPort.c ← 0; Cycle[]};
lc => {rootPort.lc ← Basics.DoubleShift[[lc[080000000h]], -rootPort.fieldStart-count].lc; Cycle[];
rootPort.lc ← 0; Cycle[]};
ENDCASE => ERROR
ELSE
SELECT port.levelType
FROM
l => {port.l ← L; Cycle[]; port.l ← H; Cycle[]};
b => {port.b ← TRUE; Cycle[]; port.b ← FALSE; Cycle[]};
ENDCASE => ERROR
}
ELSE
IF port#
NIL
THEN SELECT port.levelType
FROM
l => port.l ← L;
ls => {};
b => port.b ← port=clockAPort OR port=clockBPort;
bs => {};
c => port.c ← 0;
lc => port.lc ← 0;
ENDCASE;
IF port#
NIL
AND port.levelType#composite
THEN {count ← 0; rootPort ← port}
ELSE count ← count+1;
};
directionality: ICTest.Directionality ← force;
probe: INT ← 1;
count: NAT ← 0;
lastPin: NAT ← 0;
a: ICTest.Assignment;
rootPort: Ports.Port;
clockAPort: Ports.Port ← IF clockAName#NIL THEN p[Ports.PortIndex[cellType.public, clockAName]] ELSE NIL;
clockBPort: Ports.Port ← IF clockBName#NIL THEN p[Ports.PortIndex[cellType.public, clockBName]] ELSE NIL;
IF clockAPort#NIL THEN clockAPort.b ← TRUE;
IF clockBPort#NIL THEN clockBPort.b ← TRUE;
TerminalIO.PutRope["\n\nProbe Card Tester\n"];
[] ← Ports.VisitBinding[cellType.public, p, InitDrive];
FOR l: ICTest.Assignments ← assignmentList, l.rest
WHILE l#
NIL
DO
lastPin ← MAX[l.first.probeCardPin, lastPin];
ENDLOOP;
WHILE probe <= lastPin
DO
FOR l: ICTest.Assignments ← assignmentList, l.rest
WHILE l#
NIL
DO
a ← l.first;
IF a.probeCardPin = probe
THEN {
FOR l: ICTest.Groups ← groupList, l.rest
WHILE l#
NIL
DO
IF l.first.number=a.group
THEN {
directionality ← l.first.directionality;
EXIT;
}
ENDLOOP;
SELECT
TRUE
FROM
a.group=0 => {
TerminalIO.PutRope[IO.PutFR["Pin %g is unused, %g\n", IO.int[probe], IO.rope[a.name]]];
probe ← probe+1;
};
directionality=acquire => {
TerminalIO.PutRope[IO.PutFR["Pin %g is acquire only\n", IO.int[probe]]];
probe ← probe+1;
directionality ← force;
};
ENDCASE => {
TerminalIO.PutRope[IO.PutFR["Ready to test pin %g, %g ...", IO.int[probe], IO.rope[a.name]]];
SELECT Rope.Fetch[TerminalIO.RequestRope[""]]
FROM
'b, 'B => {
probe ← probe-1;
TerminalIO.PutRope["\n"];
};
'j, 'J => {
--jump
probe ← TerminalIO.RequestInt["\nJump to pin: "];
IF probe < 1 THEN probe ← 1;
IF probe >LAST[ICTest.ProbeCardPin] THEN probe ← LAST[ICTest.ProbeCardPin];
LOOP;
};
'q, 'Q => GOTO quit;
'r, 'R => probe ← probe; --redo
ENDCASE => {
probe ← probe+1;
};
[] ← Ports.VisitBinding[cellType.public, p, EachPair];
TerminalIO.PutRope["done\n"];
};
EXIT;
};
REPEAT
FINISHED => {
TerminalIO.PutRope[IO.PutFR["Pin %g not found\n", IO.int[probe]]];
probe ← probe+1;
};
ENDLOOP;
ENDLOOP;
};
END.