<> <> <> <> <<>> <> <> DIRECTORY CD USING [Number, Rect], CoreGeometry USING [CellType, Decoration, Rect, Transformation, Wire], Rope USING [ROPE], TNT USING [TNT]; Drc: CEDAR DEFINITIONS ~ BEGIN Transf: TYPE ~ CoreGeometry.Transformation; CoreCell: TYPE ~ CoreGeometry.CellType; Layout: TYPE ~ CoreGeometry.Decoration; Wire: TYPE ~ CoreGeometry.Wire; Rect: TYPE ~ CoreGeometry.Rect; <> CheckDesignRules: PUBLIC PROC [cell: CoreCell, external: Wire, tech: Tech, stopFlag: REF BOOL, layout: Layout] RETURNS [quantity: CARDINAL _ 0]; < NIL. Design rule violations are flagged in the Core cell using the property DRV (Design Rule Violation) with key DRVkey = $DrcError. The property DRV is put only on cells having at least one violation.>> <> <> coreInconsistent: ERROR [reason: Rope.ROPE, torch: REF ANY]; <> DRV: TYPE ~ REF DesignRuleViolation; DRVkey: ATOM; DesignRuleViolation: TYPE ~ RECORD [count: INT _ 0, places: LIST OF ErrorRect]; ErrorRect: TYPE ~ RECORD [r: CD.Rect, msg: Rope.ROPE]; <> State: PRIVATE TYPE ~ REF StateRec; StateRec: PRIVATE TYPE ~ RECORD [ tech: Tech, -- technology dependent part nt: TNT.TNT, -- neighbourhood table abort: REF BOOL, -- is graceful globalErrorCount: CARDINAL _ 0, -- the number of errors in this run wireCreationCount: CARDINAL _ 1, -- for debugging attributes: CoreGeometry.Decoration]; -- key for geometry WireInstance: PRIVATE TYPE ~ RECORD [local, global: Wire, transf: Transf]; WirePairProc: PRIVATE TYPE ~ PROC [cell: CoreCell, w1, w2: WireInstance, state: State]; <> WireProc: PRIVATE TYPE ~ PROC [cell: CoreCell, w: Wire, state: State]; CellProc: PRIVATE TYPE ~ PROC [cell: CoreCell, state: State]; Tech: PUBLIC TYPE ~ RECORD [ checkedBy: PUBLIC ATOM, maxSeparation: PUBLIC CD.Number _ LAST [CD.Number], lambda: CD.Number, -- creature comfort for debugging verifyWire: WireProc, verifyWirePair: WirePairProc, verifyCell: CellProc _ NIL]; <> MarkError: PRIVATE PROC [obj: CoreCell, state: State, e: ErrorRect]; AtomicWireHull: PRIVATE PROC [w: WireInstance, state: State] RETURNS [h: Rect] END.