Drc.mesa
Copyright Ó 1985, 1986, 1987 by Xerox Corporation. All rights reserved.
Written by gbb, January 12, 1987 11:47:17 am PST
gbb March 27, 1987 12:10:17 pm PST
Genista is the Grandson of Spinifex. It is a hierarchical design rule checker that monkeys around in a Core design and tries to find all the ChipNDale geometry in order to check as many design rules as it possibly can.
Gli uomini vollero piuttosto le tenebre che la luce (Giovanni, III, 19.)
DIRECTORY
CD USING [Number, Rect],
CoreGeometry USING [CellType, Decoration, Rect, Transformation, Wire],
Rope USING [ROPE],
TNT USING [TNT];
Drc: CEDAR DEFINITIONS
~
BEGIN
Transf: TYPE ~ CoreGeometry.Transformation;
CoreCell: TYPE ~ CoreGeometry.CellType;
Layout: TYPE ~ CoreGeometry.Decoration;
Wire: TYPE ~ CoreGeometry.Wire;
Rect: TYPE ~ CoreGeometry.Rect;
DRC
CheckDesignRules:
PUBLIC
PROC [cell: CoreCell, external: Wire, tech: Tech, stopFlag:
REF
BOOL, layout: Layout]
RETURNS [quantity:
CARDINAL ← 0];
cell and its subcells are verified, except the cells with property $DoNotDRC <> NIL. Design rule violations are flagged in the Core cell using the property DRV (Design Rule Violation) with key DRVkey = $DrcError. The property DRV is put only on cells having at least one violation.
The stopFlag is tested periodically. If it is TRUE Drc stops. This parameter is required because it is the only way the client can know whether the DRC was aborted.
The return parameter quantity contains the number of errors found.
coreInconsistent: ERROR [reason: Rope.ROPE, torch: REF ANY];
Access to violations
DRV: TYPE ~ REF DesignRuleViolation;
DRVkey: ATOM;
DesignRuleViolation: TYPE ~ RECORD [count: INT ← 0, places: LIST OF ErrorRect];
ErrorRect: TYPE ~ RECORD [r: CD.Rect, msg: Rope.ROPE];
Types for writing the technology dependent part
State: PRIVATE TYPE ~ REF StateRec;
StateRec: PRIVATE TYPE ~ RECORD [
tech: Tech, -- technology dependent part
nt: TNT.TNT, -- neighbourhood table
abort: REF BOOL, -- is graceful
globalErrorCount: CARDINAL ← 0, -- the number of errors in this run
wireCreationCount: CARDINAL ← 1, -- for debugging
attributes: CoreGeometry.Decoration]; -- key for geometry
WireInstance: PRIVATE TYPE ~ RECORD [local, global: Wire, transf: Transf];
WirePairProc:
PRIVATE
TYPE ~
PROC [cell: CoreCell, w1, w2: WireInstance, state: State];
w1 and w2 are the internal wires, aw1 and aw2 are their actual values for connectivity determination; transf1 and transf2 are the transformations of the wires. In other words, the passed wires are instances.
WireProc: PRIVATE TYPE ~ PROC [cell: CoreCell, w: Wire, state: State];
CellProc: PRIVATE TYPE ~ PROC [cell: CoreCell, state: State];
Tech:
PUBLIC
TYPE ~
RECORD [
checkedBy:
PUBLIC
ATOM,
maxSeparation:
PUBLIC
CD.Number ←
LAST [
CD.Number],
lambda:
CD.Number,
-- creature comfort for debugging
verifyWire: WireProc,
verifyWirePair: WirePairProc,
verifyCell: CellProc ←
NIL];
Semantic detail: the procedures are called in the above order. In particular, the cell procedure can assume that the wire procedure has already been called for the cell. The cell procedure is a hack circumvent inadequacies in the extraction software.
MarkError: PRIVATE PROC [obj: CoreCell, state: State, e: ErrorRect];
AtomicWireHull: PRIVATE PROC [w: WireInstance, state: State] RETURNS [h: Rect]
END.