SinixOps.mesa
Copyright Ó 1986 by Xerox Corporation. All rights reversed.
Created by Jean-Marc Frailong June 1986
Jean-Marc Frailong June 23, 1986 1:28:16 pm PDT
Bertrand Serlet December 17, 1986 3:28:35 am PST
DIRECTORY
CD, Core, CoreClasses, CoreFlat, CoreGeometry, Rope, Sinix;
SinixOps: CEDAR DEFINITIONS = BEGIN
Theory
This interface defines utilities to explore nets in Core, to allow designation of Core structures from ChipNDale, and implements extract mode registration procedures that enable a set of CD commands (in the <SPACE-O> menu) that provide for highlighting and extraction.
As ever
Wire: TYPE ~ Core.Wire;
WireSeq: TYPE ~ Core.WireSeq;
Wires: TYPE ~ Core.Wires;
Properties: TYPE ~ Core.Properties;
CellType: TYPE ~ Core.CellType;
ROPE: TYPE ~ Core.ROPE;
CellInstance: TYPE ~ CoreClasses.CellInstance;
CellInstances: TYPE ~ CoreClasses.CellInstances;
FlatWire: TYPE ~ CoreFlat.FlatWire;
FlatWireRec: TYPE ~ CoreFlat.FlatWireRec;
FlatCellType: TYPE ~ CoreFlat.FlatCellType;
FlatCellTypeRec: TYPE ~ CoreFlat.FlatCellTypeRec;
InstancePath: TYPE ~ CoreFlat.InstancePath;
Decoration: TYPE = CoreGeometry.Decoration;
Mode: TYPE ~ Sinix.Mode;
Highlight
Low-level generation of highlighted objects
HighLightInst: PROC [instance: CoreGeometry.Instance] RETURNS [hinstance: CD.Instance];
Converts instance to highlighted instance.
HighLightListInst: PROC [instances: CoreGeometry.Instances] RETURNS [hinstances: CD.InstanceList];
Converts instance list to highlighted instance list.
HighlightDesign: PROC [design: CD.Design, highlight: REF ← NIL];
Redisplays all viewers of design.
highlight is either a CD.Instance or a CD.InstanceList. NIL removes all previous highlight.
Viewers scale to the best zoom on the highlighted area.
Core highlight
HighlightNets: PROC [decoration: Decoration, design: CD.Design, instance: CD.Instance, root: CellType, flatWires: LIST OF FlatWireRec];
Highlights recursively until icons are found.
instance specifies the origin of root.
flatWires are assumed to be canonized.
Also highlights all parents of some flatWire.
Links between Core and ChipNDale
The functions in this section permit to designate Core objects (instance or wire) through the CD selection mechanism.
IsIcon: PROC [decoration: Decoration, cell: CellType] RETURNS [BOOL];
An icon is defined as a cellType decorated with interface decoration, but that is not a recordCell.
ExtractCDInstance: PROC [instance: CD.Instance, design: CD.Design, mode: Mode] RETURNS [result: REF, props: Properties];
This version of Sinix.Extract starts from a top-level CD Instance and computes the context if necessary (currently because of satellites). 
Returned arguments have same meaning as in Sinix.Extract.
ExtractCDStack: PROC [design: CD.Design, mode: Mode] RETURNS [instance: CD.Instance, root: CellType];
Extracts all cells in the CD stack, which is assumed to be non-empty.
instance is the top-level CD instance.
root is the extraction result of the outer cell, assumed to be a CellType.
root will be NIL if there is an error. A message is printed on the terminal in that case.
CDStackToPath: PROC [design: CD.Design, mode: Mode] RETURNS [instance: CD.Instance, root: CellType, pushed: CellType, flatPushed: FlatCellTypeRec];
Converts the current pushed-in stack (assumed to be non-empty) into a CoreFlat path respective to the outermost pushed-in cell.
instance is the top-level CD instance.
root is the extraction result of the outer cell, assumed to be a CellType.
In case of failure, root will be NIL and a message has been printed on the terminal.
pushed is the outermost icon or recordCell (might be root).
flatPushed is the path from root (might be []).
SelectedCoreObjects: PROC [design: CD.Design, mode: Mode, flatCellsActuals: BOOL ← FALSE] RETURNS [instance: CD.Instance, root: CellType, pushed: CellType, flatPushed: FlatCellTypeRec, flatCells: LIST OF FlatCellTypeRec ← NIL, flatWires: LIST OF FlatWireRec ← NIL];
Returns all Core cellTypes and wires that are selected in the currently pushed-in cell.
instance is the top-level CD instance.
root is the extraction result of the outer cell, assumed to be a CellType. In case of failure, root will be NIL and a message has been printed on the terminal.
pushed is the outermost icon or recordCell (might be root).
If flatCellsActuals, actuals of flatCells are added to flatWires.
IF NOT IsIcon[pushed], flatCells and flatWires design the selected instances. Each flatWire has wireRoot=internal.
IF IsIcon[pushed], flatCells=NIL and flatWires design the selected instances. Each flatWire has wireRoot=public.
If a structured wire is selected all its sub wires also appear in flatWires.
All flatWires are canonized.
SelectedCellType: PROC [design: CD.Design, mode: Mode] RETURNS [instance: CD.Instance, root: CellType, cell: CellType, flatCell: FlatCellTypeRec, trans: CoreGeometry.Transformation];
Returns the current selected cell, assuming that the selection is unique.
trans is the transformation to apply to its decoration in order to get design coordinates.
If design was at top level, instance = the selected instance, instance.trans = trans, root = cell, flatCell = [].
If any error occurs, a message is printed on the terminal and root=NIL.
Registration of extract modes
RegisterDefaultLayoutMode: PROC [mode: Mode, technology: CD.Technology];
Associates mode and technology.
GetExtractMode: PROC [tech: REF] RETURNS [mode: Mode ← NIL];
Recover the layout extract mode associated to a technology.
tech can be a CD.Technology or an atom name of a technology.
mode must have been previously registered through RegisterDefaultLayoutMode.
RegisterModeCommands: PROC [mode: Mode, technology: CD.Technology ← NIL];
Adds 2 new entries in the Extractor menu: one for extracting, and one for highlighting.
If technology is NIL, the entry will be valid for ALL technologies.
END.