[Cyan]<DATools6.1>Extract24>SinixCMosA.mesa!3

SinixCMosA.mesa

Created by Bertrand Serlet August 15, 1985 2:09:54 pm PDT

Bertrand Serlet December 16, 1986 10:24:20 pm PST

Pradeep Sindhu December 2, 1985 6:42:40 pm PST

Barth, January 13, 1986 1:41:27 pm PST

Jean-Marc Frailong July 1, 1986 1:48:07 pm PDT

DIRECTORY

CD, CDAtomicObjects, CDBasics, CDCells, CDDirectory, CDLayers, CDProperties, CDRects, CDSymbolicObjects, CDTexts,

CMos,

Core, CoreClasses, CoreOps, CoreProperties,

CoreGeometry,

PWObjects,

Rope, Sinix, SinixOps;

SinixCMosA: CEDAR PROGRAM

IMPORTS CD, CDBasics, CDCells, CDDirectory, CDLayers, CDProperties, CDRects, CDSymbolicObjects, CDTexts, CMos, CoreClasses, CoreGeometry, CoreOps, CoreProperties, PWObjects, Rope, Sinix, SinixOps

SHARES CDCells, CDLayers, CDRects, CDSymbolicObjects, CDTexts =

BEGIN

As ever

CellType: TYPE = Core.CellType;

Wire: TYPE = Core.Wire;

Object: TYPE = CD.Object;

Properties: TYPE = Core.Properties;

ROPE: TYPE = Core.ROPE;

ROPES: TYPE = LIST OF ROPE;

Properties and extraction of common objects

mode: Sinix.Mode ← NEW [Sinix.ModeRec ← [

extractProcProp: PWObjects.RegisterProp[$CMosAExtractProc, TRUE],

decoration: CoreGeometry.CreateDecoration["CMosA"],

equalProc: Sinix.CompareProps,

instanceLayer: Sinix.DefaultInstanceLayer,

touchProc: CoreGeometry.Touch

]];

AddRect: PROC [mode: Sinix.Mode, wire: Wire, rect: CD.Rect, layer: CD.Layer] = {

instance: CoreGeometry.Instance ← [

CDRects.CreateRect[CDBasics.SizeOfRect[rect], layer], [CDBasics.BaseOfRect[rect]]

];

CoreGeometry.PutPins[mode.decoration, wire, CONS [instance, CoreGeometry.GetPins[mode.decoration, wire]]];

};

Transistors

MakeAbstract: PUBLIC PROC [abstract, represents: CD.Layer] RETURNS [sameAbstract: CD.Layer] = {

CDLayers.MakeAbstract[abstract, represents]; RETURN [abstract];

};

New layers for transistors

nsource: CD.Layer ← MakeAbstract[CD.NewLayer[CMos.cmos, $CNSource], CMos.ndif];

ndrain: CD.Layer ← MakeAbstract[CD.NewLayer[CMos.cmos, $CNDrain], CMos.ndif];

psource: CD.Layer ← MakeAbstract[CD.NewLayer[CMos.cmos, $CPSource], CMos.pdif];

pdrain: CD.Layer ← MakeAbstract[CD.NewLayer[CMos.cmos, $CPDrain], CMos.pdif];

PropsFromSatellites: PROC [obj: Object, properties: CD.PropList] RETURNS [props: Core.Properties ← NIL] = {

name: ROPE ← NIL;

FOR ropes: ROPES ← NARROW [CDProperties.GetListProp[properties, Sinix.satellitesProp]], ropes.rest WHILE ropes#NIL DO

IF name#NIL AND NOT Rope.Equal[ropes.first, name] THEN SIGNAL Sinix.FusionPropMismatch[CDDirectory.Name[obj], CoreOps.nameProp, name, ropes.first];

name ← ropes.first;

ENDLOOP;

IF name#NIL THEN props ← CoreProperties.Props[[CoreOps.nameProp, name]];

};

ExtractTransistor: Sinix.ExtractProc = {

size: CD.Position = CDBasics.SizeOfRect[obj.bbox];

cellType: CellType;

lambda: CD.Number = CMos.lambda;

ext: CD.Number = 2*lambda;

wellSurr: CD.Number ← 0;

innerX: CD.Number ← 0;

dif: CD.Layer ← IF obj.layer=CMos.wpdif OR obj.layer=CMos.pdif THEN CMos.pdif ELSE CMos.ndif;

gateWire, sourceWire, drainWire: Wire;

IF obj.layer=CMos.wpdif OR obj.layer=CMos.wndif THEN {

wellSurr ← CMos.wellSurround;

innerX ← CMos.wellSurround-ext;

};

cellType ← CoreClasses.CreateTransistor[[

type: IF dif=CMos.pdif THEN pE ELSE nE,

length: (size.y-2*ext-2*wellSurr)/lambda-2,

width: (size.x-2*ext-2*innerX)/lambda]];

props ← PropsFromSatellites[obj, properties];

gateWire ← cellType.public[0];

sourceWire ← cellType.public[1];

drainWire ← cellType.public[2];

IF obj.layer=CMos.wpdif OR obj.layer=CMos.wndif THEN {

AddRect[mode, sourceWire,

[x1: ext, x2: size.x-2*CMos.wellSurround+ext, y1: 0, y2: ext],

IF dif=CMos.pdif THEN psource ELSE nsource];

AddRect[mode, drainWire,

[x1: ext, x2: size.x-2*CMos.wellSurround+ext, y1: size.y-2*CMos.wellSurround-ext, y2: size.y-2*CMos.wellSurround],

IF dif=CMos.pdif THEN pdrain ELSE ndrain];

} ELSE {

AddRect[mode, sourceWire,

[x1: ext, x2: size.x-ext, y1: 0, y2: ext],

IF dif=CMos.pdif THEN psource ELSE nsource];

AddRect[mode, drainWire,

[x1: ext, x2: size.x-ext, y1: size.y-ext, y2: size.y],

IF dif=CMos.pdif THEN pdrain ELSE ndrain];

};

FOR rList: CDAtomicObjects.DrawList ← NARROW [obj.specific, CDAtomicObjects.AtomicObsSpecific].rList, rList.rest WHILE rList#NIL DO

rect: CD.Rect ← rList.first.r;

layer: CD.Layer ← rList.first.layer;

SELECT layer FROM

CMos.ndif => {};

CMos.pdif => {};

CMos.pol => AddRect[mode, gateWire, rect, CMos.pol];

CMos.nwell, CMos.pwell => {};

ENDCASE => ERROR;

ENDLOOP;

CoreGeometry.PutObject[mode.decoration, cellType, obj];

result ← cellType;

};

ExtractTransistorL: Sinix.ExtractProc = {

size: CD.Position = CDBasics.SizeOfRect[obj.bbox];

cellType: CellType;

lambda: CD.Number = CMos.lambda;

wellSurround: CD.Number = CMos.wellSurround;

ext: CD.Number = 2*lambda;

wellSurr: CD.Number ← 0;

innerX: CD.Number ← 0;

gateWire, sourceWire, drainWire: Wire;

dif: CD.Layer ← IF obj.layer=CMos.wpdif OR obj.layer=CMos.pdif THEN CMos.pdif ELSE CMos.ndif;

IF obj.layer=CMos.wpdif OR obj.layer=CMos.wndif THEN {

wellSurr ← wellSurround;

innerX ← wellSurround-ext;

};

cellType ← CoreClasses.CreateTransistor[[

type: IF obj.layer=CMos.wpdif OR obj.layer=CMos.pdif THEN pE ELSE nE,

length: 2,

width: (size.x+size.y-2*innerX-2*wellSurr)/lambda - 12]];

props ← PropsFromSatellites[obj, properties];

gateWire ← cellType.public[0];

sourceWire ← cellType.public[1];

drainWire ← cellType.public[2];

source is the smallest diff

IF obj.layer=CMos.wpdif OR obj.layer=CMos.wndif THEN {

AddRect[mode, sourceWire,

[x1: ext, x2: size.x-wellSurr-9*lambda, y1: 6*lambda, y2: 8*lambda],

IF dif=CMos.pdif THEN psource ELSE nsource];

AddRect[mode, sourceWire,

[x1: size.x-wellSurr-11*lambda, x2: size.x-wellSurr-9*lambda, y1: 6*lambda, y2: size.y-innerX-ext-wellSurr],

IF dif=CMos.pdif THEN psource ELSE nsource];

AddRect[mode, drainWire,

[x1: ext, x2: size.x-wellSurr-3*lambda, y1: 0, y2: 2*lambda],

IF dif=CMos.pdif THEN pdrain ELSE ndrain];

AddRect[mode, drainWire,

[x1: size.x-wellSurr-5*lambda, x2: size.x-wellSurr-3*lambda, y1: 0, y2: size.y-innerX-ext-wellSurr],

IF dif=CMos.pdif THEN pdrain ELSE ndrain];

} ELSE {

AddRect[mode, sourceWire,

[x1: innerX+ext, x2: size.x-wellSurr-6*lambda, y1: wellSurr+6*lambda, y2: wellSurr+8*lambda],

IF dif=CMos.pdif THEN psource ELSE nsource];

AddRect[mode, sourceWire,

[x1: size.x-wellSurr-8*lambda, x2: size.x-wellSurr-6*lambda, y1: wellSurr+6*lambda, y2: size.y-innerX-ext],

IF dif=CMos.pdif THEN psource ELSE nsource];

AddRect[mode, drainWire,

[x1: innerX+ext, x2: size.x-wellSurr, y1: wellSurr, y2: wellSurr+2*lambda],

IF dif=CMos.pdif THEN pdrain ELSE ndrain];

AddRect[mode, drainWire,

[x1: size.x-wellSurr-2*lambda, x2: size.x-wellSurr, y1: wellSurr, y2: size.y-innerX-ext],

IF dif=CMos.pdif THEN pdrain ELSE ndrain];

};

FOR rList: CDAtomicObjects.DrawList ← NARROW [obj.specific, CDAtomicObjects.AtomicObsSpecific].rList, rList.rest WHILE rList#NIL DO

rect: CD.Rect ← rList.first.r;

layer: CD.Layer ← rList.first.layer;

SELECT layer FROM

CMos.pol => AddRect[mode, gateWire, rect, CMos.pol];

CMos.ndif => {};

CMos.pdif => {};

CMos.nwell, CMos.pwell => {};

ENDCASE => ERROR;

ENDLOOP;

CoreGeometry.PutObject[mode.decoration, cellType, obj];

result ← cellType;

};

Initialization

Atomic: PROC [className: ATOM] = {

class: CD.ObjectClass = CD.FetchObjectClass[className, CMos.cmos];

CDProperties.PutProp[class, mode.extractProcProp, $ExtractAtomic];

};

Layer properties

CDProperties.PutLayerProp[CMos.pwell, $Well, $PWell];

CDProperties.PutLayerProp[CMos.nwell, $Well, $NWell];

CDProperties.PutLayerProp[CMos.ndif, $RoutingLayer, $RoutingLayer];

CDProperties.PutLayerProp[CMos.pdif, $RoutingLayer, $RoutingLayer];

CDProperties.PutLayerProp[CMos.pol, $RoutingLayer, $RoutingLayer];

CDProperties.PutLayerProp[CMos.met, $RoutingLayer, $RoutingLayer];

CDProperties.PutLayerProp[CMos.met2, $RoutingLayer, $RoutingLayer];

Highlight for this technology

SinixOps.RegisterDefaultLayoutMode[mode, CMos.cmos];

Registering extract procs

Sinix.RegisterExtractProc[$CMosAExtractTransistor, ExtractTransistor];

Sinix.RegisterExtractProc[$CMosAExtractTransistorL, ExtractTransistorL];

Cells, Pins

CDProperties.PutProp[CDCells.pCellClass, mode.extractProcProp, $ExtractCell];

CDProperties.PutProp[CDSymbolicObjects.pinClass, mode.extractProcProp, $ExtractPin];

CDProperties.PutProp[CDSymbolicObjects.segmentClass, mode.extractProcProp, $ExtractPin];

CDProperties.PutProp[CDSymbolicObjects.markClass, mode.extractProcProp, $ExtractPin];

Rectangles

CDProperties.PutProp[CDRects.bareRectClass, mode.extractProcProp, $ExtractRect];

Contacts

Atomic[className: $CSimpleCon];

Atomic[className: $CWellSimpleCon];

Atomic[className: $CButtingCont];

Atomic[className: $CWellButtingCont];

Atomic[className: $CVia];

Atomic[className: $CDifShortCon];

Atomic[className: $CWellDifShortCon];

Diffusion wires

Atomic[className: $CMosPDifRect];

Transistors

CDProperties.PutProp[CD.FetchObjectClass[$CTrans, CMos.cmos], mode.extractProcProp, $CMosAExtractTransistor];

CDProperties.PutProp[CD.FetchObjectClass[$CWellTrans, CMos.cmos], mode.extractProcProp, $CMosAExtractTransistor];

Angle Transistors

CDProperties.PutProp[CD.FetchObjectClass[$CLTrans, CMos.cmos], mode.extractProcProp, $CMosAExtractTransistorL];

CDProperties.PutProp[CD.FetchObjectClass[$CLWellTrans, CMos.cmos], mode.extractProcProp, $CMosAExtractTransistorL];

Texts

CDProperties.PutProp[CDTexts.rigidTextClass, mode.extractProcProp, $ExtractNull];

CDProperties.PutProp[CDTexts.flipTextClass, mode.extractProcProp, $ExtractNull];

END.