RawFoo.cm

Install Boole

Run TestBoole

← RosemaryImpl.sizeHackEnable ← TRUE

Run SinixRawCMosBImpl

← &design ← PW.OpenDesign["bar"]

← SinixRawCMosBImpl.Mark[&design]

← CDProperties.PutProp[CDDirectory.Fetch[&design, "DoNotFlatten"].object, $RawFlatten, NIL]

← &obj ← CDDirectory.Fetch[&design, "Test"].object

← &ct ← Sinix.Extract[&obj, SinixRawCMosB.mode, NIL, NEW [INT ← 0]].result

← CoreOps.Print[&ct]

← &source ← LayoutCheckpoint.Retrieve["foo"]

← &new ← SinixRawCMosBImpl.MatchSourceToExtracted[&source.public, &ct, "NewFoo"]

← CoreOps.Print[&new]

← CoreOps.Print[&new.data[0].type]

← CoreOps.Print[&new.data[0].type.data[0].type]

← CoreOps.Print[&new.data[0].type.data[0].type.data[3].type]

-- Note that VRef$0$ is attached to transistors!!

← &w0 ← CoreOps.FindWire[&new.data[0].type.data[0].type.data[3].type.public, "VRef$0$"]

← &w1 ← CoreClasses.CorrespondingActual[&new.data[0].type.data[0].type.data[3], &w0]

← CoreOps.GetFullWireNames[&new.data[0].type.data[0].type.data.internal, &w1]

← &w2 ← CoreClasses.CorrespondingActual[&new.data[0].type.data[0], &w1]

← CoreOps.GetFullWireNames[&new.data[0].type.data.internal, &w2]

← &w3 ← CoreClasses.CorrespondingActual[&new.data[0], &w2]

← CoreOps.GetFullWireNames[&new.data.internal, &w3]

-- Note that this wire is really VRef (at top level)

← CoreIO.ReportSaveCellType[&new]

← &ct ← CoreIO.RestoreCellType["NewFoo"]

← &ct ← CoreOps.Recast[&ct]

← CoreOps.Print[&ct.data[0].type.data[0].type.data[3].type]

-- Note that VRef$0$ is attached to transistors!!

← &w0 ← CoreOps.FindWire[&ct.data[0].type.data[0].type.data[3].type.public, "VRef$0$"]

← &w1 ← CoreClasses.CorrespondingActual[&ct.data[0].type.data[0].type.data[3], &w0]

← CoreOps.GetFullWireNames[&ct.data[0].type.data[0].type.data.internal, &w1]

← &w2 ← CoreClasses.CorrespondingActual[&ct.data[0].type.data[0], &w1]

← CoreOps.GetFullWireNames[&ct.data[0].type.data.internal, &w2]

← &w3 ← CoreClasses.CorrespondingActual[&ct.data[0], &w2]

← CoreOps.GetFullWireNames[&ct.data.internal, &w3]

-- Note that this wire is really VRef (at top level)

← Rosemary.SetFixedWire[CoreOps.FindWire[&ct.public, "Vdd"], H]

← Rosemary.SetFixedWire[CoreOps.FindWire[&ct.public, "Gnd"], L]

← Rosemary.SetFixedWire[CoreOps.FindWire[&ct.public, "phiA"], H]

← Rosemary.SetFixedWire[CoreOps.FindWire[&ct.public, "phiB"], H]

← Rosemary.SetFixedWire[CoreOps.FindWire[&ct.public, "VRef"], H]

← Ports.InitPort[wire: &ct.public[0], levelType: l]

← Ports.InitPort[wire: &ct.public[1], levelType: l]

← Ports.InitPort[wire: &ct.public[2], levelType: l]

← Ports.InitPort[wire: &ct.public[3], levelType: l]

← Ports.InitPort[wire: &ct.public[4], levelType: l]

← Ports.InitPort[wire: &ct.public[5], levelType: l]

← Ports.InitPort[wire: &ct.public[6], levelType: l]

← Ports.InitPort[wire: &ct.public[7], levelType: l]

← Ports.InitPort[wire: &ct.public[8], levelType: l]

← Ports.InitPort[wire: &ct.public[9], levelType: l]

← Ports.InitPort[wire: &ct.public[10], levelType: l]

← Ports.InitTesterDrive[wire: CoreOps.FindWire[&ct.public, "a"], initDrive: force]

← Ports.InitTesterDrive[wire: CoreOps.FindWire[&ct.public, "b"], initDrive: force]

← Ports.InitTesterDrive[wire: CoreOps.FindWire[&ct.public, "c"], initDrive: force]

← Ports.InitTesterDrive[wire: CoreOps.FindWire[&ct.public, "d"], initDrive: force]

← Ports.InitTesterDrive[wire: CoreOps.FindWire[&ct.public, "r"], initDrive: expect]

← Ports.InitTesterDrive[wire: CoreOps.FindWire[&ct.public, "ab"], initDrive: expect]

← &sim ← RosemaryUser.TestProcedureViewer [cellType: &ct, testButtons: LIST["AlpsTest"], name: "Alps Transistor Tester", displayWires: RosemaryUser.DisplayPortLeafWires[&ct, [path: [length: 0, bits: ALL[FALSE]], recastCount: 0]], graphWires: NIL, cutSet: NIL, historySize: 0, steady: FALSE, recordDeltas: TRUE]

-- Now, do a "t VRef" and see that VRef appears as connected to nothing. Also do a "t /0(Test)/0(DoNotFlatten).[53]" to see that in fact VRef is gate of something!