EURawSim.mesa
Copyright © 1985 by Xerox Corporation. All rights reversed.
Created by Bertrand Serlet July 31, 1985 3:03:17 pm PDT
Last edited by Bertrand Serlet November 24, 1986 7:03:14 pm PST
Barth, September 26, 1986 2:59:10 pm PDT
Louis Monier June 19, 1986 11:54:42 pm PDT
Last Edited by: Louis Monier October 20, 1986 10:25:48 am PDT
Last Edited by: Gasbarro October 1, 1986 6:05:58 pm PDT
DIRECTORY
Core, CoreFlat, Rope, Rosemary, RosemaryUser, Ports;
EURawSim:
CEDAR
PROGRAM
IMPORTS CoreFlat, Rosemary, RosemaryUser, Ports =
BEGIN OPEN Core;
Vdd, Gnd, PadVdd, PadGnd, PhA, PhB,
DPRejectB, DPData, -- 32 bits
KBus, -- 32 bits
EURdFromPBus3AB, EUWriteToPBus3AB,
EUAluOp2AB, -- 4 bits
EUCondSel2AB, -- 4 bits
EUCondition2B,
DShA, DShB, DShRd, DShWt, DShIn, DShOut, DHold, DStAd: NAT ← LAST[NAT];
allOnes: LONG CARDINAL ← LOOPHOLE[LONG[-1]];
Initialize:
PROC [p: Ports.Port, public: Wire] = {
InitializePublic[public];
p[DPRejectB].b ← FALSE;
p[DShA].b ← p[DShB].b ← TRUE; -- hack to clean up the ShReg.
p[DShRd].b ← p[DShWt].b ← p[DShIn].b ← p[DHold].b ← FALSE;
p[DStAd].c ← 0;
p[EUCondSel2AB].c ← 0; -- false
p[EUAluOp2AB].c ← 0; -- 0
p[EURdFromPBus3AB].b ← FALSE; -- don't read data from PBus
p[EUWriteToPBus3AB].b ← FALSE; -- and don't write onto PBus during PhB
p[DShOut].b ← FALSE;
p[DShOut].d ← none;
p[EUCondition2B].b ← FALSE;
p[EUCondition2B].d ← none;
p[KBus].d ← none;
p[DPData].d ← none;
};
InitializePublic:
PROC [public: Core.Wire] = {
[Vdd, Gnd, PadVdd, PadGnd, PhA, PhB, DPRejectB, DPData] ← Ports.PortIndexes[public, "Vdd", "Gnd", "PadVdd", "PadGnd", "PhA", "PhB", "DPRejectB", "DPData"];
[KBus, EURdFromPBus3AB, EUWriteToPBus3AB, EUAluOp2AB, EUCondSel2AB, EUCondition2B] ← Ports.PortIndexes[public, "KBus", "EURdFromPBus3AB", "EUWriteToPBus3AB", "EUAluOp2AB", "EUCondSel2AB", "EUCondition2B"];
[DShA, DShB, DShRd, DShWt, DShIn, DShOut, DHold, DStAd] ←
Ports.PortIndexes[public, "DShA", "DShB", "DShRd", "DShWt", "DShIn", "DShOut", "DHold", "DStAd"];
[] ← Rosemary.SetFixedWire[public[Vdd], H];
[] ← Rosemary.SetFixedWire[public[Gnd], L];
[] ← Rosemary.SetFixedWire[public[PadVdd], H];
[] ← Rosemary.SetFixedWire[public[PadGnd], L];
[] ← Ports.InitTesterDrive[public[PhA], force];
[] ← Ports.InitTesterDrive[public[PhB], force];
[] ← Ports.InitTesterDrive[public[DPRejectB], force];
[] ← Ports.InitPort[public[DPData], lc];
[] ← Ports.InitTesterDrive[public[DPData], expect];
[] ← Ports.InitPort[public[KBus], lc];
[] ← Ports.InitTesterDrive[public[KBus], force];
[] ← Ports.InitTesterDrive[public[EURdFromPBus3AB], force];
[] ← Ports.InitTesterDrive[public[EUWriteToPBus3AB], force];
[] ← Ports.InitPort[public[EUAluOp2AB], c];
[] ← Ports.InitTesterDrive[public[EUAluOp2AB], force];
[] ← Ports.InitPort[public[EUCondSel2AB], c];
[] ← Ports.InitTesterDrive[public[EUCondSel2AB], force];
[] ← Ports.InitTesterDrive[public[EUCondition2B], expect];
[] ← Ports.InitTesterDrive[public[DShA], force];
[] ← Ports.InitTesterDrive[public[DShB], force];
[] ← Ports.InitTesterDrive[public[DShRd], force];
[] ← Ports.InitTesterDrive[public[DShWt], force];
[] ← Ports.InitTesterDrive[public[DShIn], force];
[] ← Ports.InitTesterDrive[public[DHold], force];
[] ← Ports.InitPort[public[DStAd], c];
[] ← Ports.InitTesterDrive[public[DStAd], force];
[] ← Ports.InitTesterDrive[public[DShOut], none];
};
Phase: TYPE = {A, B};
constAdr: NAT ← 132;
junkAdr: NAT ← 128;
IFUAdr: NAT ← 129;
fieldAdr: NAT ← 131;
DoPh:
PROC [p: Ports.Port,
Eval:
PROC, ph: Phase] = {
-- Invariants
IF PhA=0 AND PhB=0 THEN ERROR; -- port indexes not initialized
-- On PhA the chip always drives the PBus, so we check that the tester is not driving
IF ph=A AND p[DPData].d=force THEN ERROR;
-- appropriate clock up
p[PhA].b ← ph=A; p[PhB].b ← ph=B; Eval[];
-- both clocks down
p[PhA].b ← FALSE; p[PhB].b ← FALSE; Eval[ ! Ports.CheckError => RESUME];
};
Ignore: PROC [p: Ports.Port, port: NAT] ~ {p[port].d ← none};
Force: PROC [p: Ports.Port, port: NAT, val: LONG CARDINAL] ~ {p[port].d ← force; p[port].lc ← val};
Expect: PROC [p: Ports.Port, port: NAT, val: LONG CARDINAL] ~ {p[port].d ← expect; p[port].lc ← val};
PackK:
PROC [a, b:
NAT ← constAdr,
c: NAT ← junkAdr,
st3AisC: BOOL ← FALSE,
aluL, aluR, st2A: NAT ← 0] RETURNS [k: LONG CARDINAL] ~ {
k ← (((((LONG[a]*256+LONG[b])*256+LONG[c])*2+(IF st3AisC THEN 1 ELSE 0))*4+aluL)*8+aluR)*4+st2A;
};
FromPtoK:
PROC [p: Ports.Port,
Eval:
PROC, val:
LONG
CARDINAL] ~ {
p[EURdFromPBus3AB].b ← TRUE;
p[EUWriteToPBus3AB].b ← FALSE;
Force[p, KBus, PackK[c: IFUAdr]]; -- cBus->IFU on next PhA
Force[p, DPData, val];
DoPh[p, Eval, B]; -- Cycle 0: dataIn ← val
p[EURdFromPBus3AB].b ← TRUE; -- because of a bug, needed to let...
p[EUWriteToPBus3AB].b ← TRUE; -- ... the cBus driver drive the bus
Ignore[p, DPData];
Expect[p, KBus, val];
DoPh[p, Eval, A]; -- Cycle 1: KBus ← cBus ← val
p[EURdFromPBus3AB].b ← FALSE;
p[EUWriteToPBus3AB].b ← FALSE;
};
LoopTest: RosemaryUser.TestProc = {
Initialize[p, cellType.public];
FromPtoK[p, Eval,000000000H];
FromPtoK[p, Eval,0FFFFFFFFH];
};
ExerciseRose:
PUBLIC
PROC [ct: CellType, cutSets:
LIST
OF Rope.
ROPE ←
NIL]
RETURNS [tester: RosemaryUser.Tester] = {
InitializePublic[ct.public];
-- If testing the cellType
tester ← RosemaryUser.TestProcedureViewer[
cellType: ct,
testButtons: LIST["LoopTest"],
name: "EUTest",
displayWires: RosemaryUser.DisplayPortLeafWires[ct],
cutSet: CoreFlat.CreateCutSet[cellTypes: cutSets],
steady: FALSE];
};
RosemaryUser.RegisterTestProc["LoopTest", LoopTest];
END.