Install Boole Run TestBoole _ RosemaryImpl.sizeHackEnable _ TRUE Run SinixRawCMosBImpl _ &design _ PW.OpenDesign["bar"] _ SinixRawCMosBImpl.Mark[&design] _ CDProperties.PutProp[CDDirectory.Fetch[&design, "DoNotFlatten"].object, $RawFlatten, NIL] _ &obj _ CDDirectory.Fetch[&design, "Test"].object _ &ct _ Sinix.Extract[&obj, SinixRawCMosB.mode, NIL, NEW [INT _ 0]].result _ &source _ LayoutCheckpoint.Retrieve["foo"] _ &new _ SinixRawCMosBImpl.MatchSourceToExtracted[&source.public, &ct, "NewFoo"] _ CoreOps.Print[&new.data[0].type.data[0].type.data[3].type] _ &w0 _ CoreOps.FindWire[&new.data[0].type.data[0].type.data[3].type.public, "VRef$0$"] _ &w1 _ CoreClasses.CorrespondingActual[&new.data[0].type.data[0].type.data[3], &w0] _ CoreOps.GetFullWireNames[&new.data[0].type.data[0].type.data.internal, &w1] _ &w2 _ CoreClasses.CorrespondingActual[&new.data[0].type.data[0], &w1] _ CoreOps.GetFullWireNames[&new.data[0].type.data.internal, &w2] _ &w3 _ CoreClasses.CorrespondingActual[&new.data[0], &w2] _ CoreOps.GetFullWireNames[&new.data.internal, &w3] _ CoreIO.ReportSaveCellType[&new] _ &ct _ CoreIO.RestoreCellType["NewFoo"] _ &ct _ CoreOps.Recast[&ct] _ CoreOps.Print[&ct.data[0].type.data[0].type.data[3].type] _ &w0 _ CoreOps.FindWire[&ct.data[0].type.data[0].type.data[3].type.public, "VRef$0$"] _ &w1 _ CoreClasses.CorrespondingActual[&ct.data[0].type.data[0].type.data[3], &w0] _ CoreOps.GetFullWireNames[&ct.data[0].type.data[0].type.data.internal, &w1] _ &w2 _ CoreClasses.CorrespondingActual[&ct.data[0].type.data[0], &w1] _ CoreOps.GetFullWireNames[&ct.data[0].type.data.internal, &w2] _ &w3 _ CoreClasses.CorrespondingActual[&ct.data[0], &w2] _ CoreOps.GetFullWireNames[&ct.data.internal, &w3] _ Rosemary.SetFixedWire[CoreOps.FindWire[&ct.public, "Vdd"], H] _ Rosemary.SetFixedWire[CoreOps.FindWire[&ct.public, "Gnd"], L] _ Rosemary.SetFixedWire[CoreOps.FindWire[&ct.public, "phiA"], H] _ Rosemary.SetFixedWire[CoreOps.FindWire[&ct.public, "phiB"], H] _ Rosemary.SetFixedWire[CoreOps.FindWire[&ct.public, "VRef"], H] _ Ports.InitPort[wire: &ct.public[0], levelType: l] _ Ports.InitPort[wire: &ct.public[1], levelType: l] _ Ports.InitPort[wire: &ct.public[2], levelType: l] _ Ports.InitPort[wire: &ct.public[3], levelType: l] _ Ports.InitPort[wire: &ct.public[4], levelType: l] _ Ports.InitPort[wire: &ct.public[5], levelType: l] _ Ports.InitPort[wire: &ct.public[6], levelType: l] _ Ports.InitPort[wire: &ct.public[7], levelType: l] _ Ports.InitPort[wire: &ct.public[8], levelType: l] _ Ports.InitPort[wire: &ct.public[9], levelType: l] _ Ports.InitPort[wire: &ct.public[10], levelType: l] _ Ports.InitTesterDrive[wire: CoreOps.FindWire[&ct.public, "a"], initDrive: force] _ Ports.InitTesterDrive[wire: CoreOps.FindWire[&ct.public, "b"], initDrive: force] _ Ports.InitTesterDrive[wire: CoreOps.FindWire[&ct.public, "c"], initDrive: force] _ Ports.InitTesterDrive[wire: CoreOps.FindWire[&ct.public, "d"], initDrive: force] _ Ports.InitTesterDrive[wire: CoreOps.FindWire[&ct.public, "r"], initDrive: expect] _ Ports.InitTesterDrive[wire: CoreOps.FindWire[&ct.public, "ab"], initDrive: expect] _ &sim _ RosemaryUser.TestProcedureViewer [cellType: &ct, testButtons: LIST["AlpsTest"], name: "Alps Transistor Tester", displayWires: RosemaryUser.DisplayPortLeafWires[&ct, [path: [length: 0, bits: ALL[FALSE]], recastCount: 0]], graphWires: NIL, cutSet: NIL, historySize: 0, steady: FALSE, recordDeltas: TRUE] 4RawFoo.cm Bertrand Serlet November 23, 1986 1:07:11 am PST _ CoreOps.Print[&ct] _ CoreOps.Print[&new] _ CoreOps.Print[&new.data[0].type] _ CoreOps.Print[&new.data[0].type.data[0].type] -- Note that VRef$0$ is attached to transistors!! -- Note that this wire is really VRef (at top level) -- Note that VRef$0$ is attached to transistors!! -- Note that this wire is really VRef (at top level) -- Now, do a "t VRef" and see that VRef appears as connected to nothing. Also do a "t /0(Test)/0(DoNotFlatten).[53]" to see that in fact VRef is gate of something! Êÿ˜™ Icode™0—J™J˜ J˜ Jšœ Ïk˜$Jšœ˜Jšœ ˜ Jšœ!˜!Jšœ[˜[Jšœ2˜2JšœJ˜JJšœ™Jšœ,˜,JšœP˜PJšœ™Jšœ"™"Jšœ/™/Jšœ<˜