DIRECTORY Core, CoreFlat, Rope, Rosemary, RosemaryUser, Ports; EURawSim: CEDAR PROGRAM IMPORTS CoreFlat, Rosemary, RosemaryUser, Ports = BEGIN OPEN Core; Vdd, Gnd, PadVdd, PadGnd, PhA, PhB, DPRejectB, DPData, -- 32 bits KBus, -- 32 bits EURdFromPBus3AB, EUWriteToPBus3AB, EUAluOp2AB, -- 4 bits EUCondSel2AB, -- 4 bits EUCondition2B, DShA, DShB, DShRd, DShWt, DShIn, DShOut, DHold, DStAd: NAT _ LAST[NAT]; allOnes: LONG CARDINAL _ LOOPHOLE[LONG[-1]]; Initialize: PROC [p: Ports.Port, public: Wire] = { InitializePublic[public]; p[DPRejectB].b _ FALSE; p[DShA].b _ p[DShB].b _ TRUE; -- hack to clean up the ShReg. p[DShRd].b _ p[DShWt].b _ p[DShIn].b _ p[DHold].b _ FALSE; p[DStAd].c _ 0; p[EUCondSel2AB].c _ 0; -- false p[EUAluOp2AB].c _ 0; -- 0 p[EURdFromPBus3AB].b _ FALSE; -- don't read data from PBus p[EUWriteToPBus3AB].b _ FALSE; -- and don't write onto PBus during PhB p[DShOut].b _ FALSE; p[DShOut].d _ none; p[EUCondition2B].b _ FALSE; p[EUCondition2B].d _ none; p[KBus].d _ none; p[DPData].d _ none; }; InitializePublic: PROC [public: Core.Wire] = { [Vdd, Gnd, PadVdd, PadGnd, PhA, PhB, DPRejectB, DPData] _ Ports.PortIndexes[public, "Vdd", "Gnd", "PadVdd", "PadGnd", "PhA", "PhB", "DPRejectB", "DPData"]; [KBus, EURdFromPBus3AB, EUWriteToPBus3AB, EUAluOp2AB, EUCondSel2AB, EUCondition2B] _ Ports.PortIndexes[public, "KBus", "EURdFromPBus3AB", "EUWriteToPBus3AB", "EUAluOp2AB", "EUCondSel2AB", "EUCondition2B"]; [DShA, DShB, DShRd, DShWt, DShIn, DShOut, DHold, DStAd] _ Ports.PortIndexes[public, "DShA", "DShB", "DShRd", "DShWt", "DShIn", "DShOut", "DHold", "DStAd"]; [] _ Rosemary.SetFixedWire[public[Vdd], H]; [] _ Rosemary.SetFixedWire[public[Gnd], L]; [] _ Rosemary.SetFixedWire[public[PadVdd], H]; [] _ Rosemary.SetFixedWire[public[PadGnd], L]; [] _ Ports.InitTesterDrive[public[PhA], force]; [] _ Ports.InitTesterDrive[public[PhB], force]; [] _ Ports.InitTesterDrive[public[DPRejectB], force]; [] _ Ports.InitPort[public[DPData], lc]; [] _ Ports.InitTesterDrive[public[DPData], expect]; [] _ Ports.InitPort[public[KBus], lc]; [] _ Ports.InitTesterDrive[public[KBus], force]; [] _ Ports.InitTesterDrive[public[EURdFromPBus3AB], force]; [] _ Ports.InitTesterDrive[public[EUWriteToPBus3AB], force]; [] _ Ports.InitPort[public[EUAluOp2AB], c]; [] _ Ports.InitTesterDrive[public[EUAluOp2AB], force]; [] _ Ports.InitPort[public[EUCondSel2AB], c]; [] _ Ports.InitTesterDrive[public[EUCondSel2AB], force]; [] _ Ports.InitTesterDrive[public[EUCondition2B], expect]; [] _ Ports.InitTesterDrive[public[DShA], force]; [] _ Ports.InitTesterDrive[public[DShB], force]; [] _ Ports.InitTesterDrive[public[DShRd], force]; [] _ Ports.InitTesterDrive[public[DShWt], force]; [] _ Ports.InitTesterDrive[public[DShIn], force]; [] _ Ports.InitTesterDrive[public[DHold], force]; [] _ Ports.InitPort[public[DStAd], c]; [] _ Ports.InitTesterDrive[public[DStAd], force]; [] _ Ports.InitTesterDrive[public[DShOut], none]; }; Phase: TYPE = {A, B}; constAdr: NAT _ 132; junkAdr: NAT _ 128; IFUAdr: NAT _ 129; fieldAdr: NAT _ 131; DoPh: PROC [p: Ports.Port, Eval: PROC, ph: Phase] = { IF PhA=0 AND PhB=0 THEN ERROR; -- port indexes not initialized IF ph=A AND p[DPData].d=force THEN ERROR; p[PhA].b _ ph=A; p[PhB].b _ ph=B; Eval[]; p[PhA].b _ FALSE; p[PhB].b _ FALSE; Eval[ ! Ports.CheckError => RESUME]; }; Ignore: PROC [p: Ports.Port, port: NAT] ~ {p[port].d _ none}; Force: PROC [p: Ports.Port, port: NAT, val: LONG CARDINAL] ~ {p[port].d _ force; p[port].lc _ val}; Expect: PROC [p: Ports.Port, port: NAT, val: LONG CARDINAL] ~ {p[port].d _ expect; p[port].lc _ val}; PackK: PROC [a, b: NAT _ constAdr, c: NAT _ junkAdr, st3AisC: BOOL _ FALSE, aluL, aluR, st2A: NAT _ 0] RETURNS [k: LONG CARDINAL] ~ { k _ (((((LONG[a]*256+LONG[b])*256+LONG[c])*2+(IF st3AisC THEN 1 ELSE 0))*4+aluL)*8+aluR)*4+st2A; }; FromPtoK: PROC [p: Ports.Port, Eval: PROC, val: LONG CARDINAL] ~ { p[EURdFromPBus3AB].b _ TRUE; p[EUWriteToPBus3AB].b _ FALSE; Force[p, KBus, PackK[c: IFUAdr]]; -- cBus->IFU on next PhA Force[p, DPData, val]; DoPh[p, Eval, B]; -- Cycle 0: dataIn _ val p[EURdFromPBus3AB].b _ TRUE; -- because of a bug, needed to let... p[EUWriteToPBus3AB].b _ TRUE; -- ... the cBus driver drive the bus Ignore[p, DPData]; Expect[p, KBus, val]; DoPh[p, Eval, A]; -- Cycle 1: KBus _ cBus _ val p[EURdFromPBus3AB].b _ FALSE; p[EUWriteToPBus3AB].b _ FALSE; }; LoopTest: RosemaryUser.TestProc = { Initialize[p, cellType.public]; FromPtoK[p, Eval,000000000H]; FromPtoK[p, Eval,0FFFFFFFFH]; }; ExerciseRose: PUBLIC PROC [ct: CellType, cutSets: LIST OF Rope.ROPE _ NIL] RETURNS [tester: RosemaryUser.Tester] = { InitializePublic[ct.public]; tester _ RosemaryUser.TestProcedureViewer[ cellType: ct, testButtons: LIST["LoopTest"], name: "EUTest", displayWires: RosemaryUser.DisplayPortLeafWires[ct], cutSet: CoreFlat.CreateCutSet[cellTypes: cutSets], steady: FALSE]; }; RosemaryUser.RegisterTestProc["LoopTest", LoopTest]; END. @EURawSim.mesa Copyright c 1985 by Xerox Corporation. All rights reversed. Created by Bertrand Serlet July 31, 1985 3:03:17 pm PDT Last edited by Bertrand Serlet November 24, 1986 7:03:14 pm PST Barth, September 26, 1986 2:59:10 pm PDT Louis Monier June 19, 1986 11:54:42 pm PDT Last Edited by: Louis Monier October 20, 1986 10:25:48 am PDT Last Edited by: Gasbarro October 1, 1986 6:05:58 pm PDT -- Invariants -- On PhA the chip always drives the PBus, so we check that the tester is not driving -- appropriate clock up -- both clocks down -- If testing the cellType ‌تT– "cedar" styleکcodeڑœ ™ Jڑœ دmœ1™