EU.mesa
Copyright © 1985 by Xerox Corporation. All rights reserved.
Louis Monier June 2, 1986 3:52:58 pm PDT
McCreight, April 10, 1986 12:13:37 pm PST
Barth, April 19, 1986 5:23:49 pm PST
Bertrand Serlet June 7, 1986 7:10:28 pm PDT
Last Edited by: Louis Monier November 17, 1986 1:53:04 am PST
EUStateRec:
TYPE =
RECORD[
-- kitchen sink
data: REF EUTypeData ← NIL,
-- ports indexes
Vdd, Gnd, PadVdd, PadGnd, PhA, PhB, VRef,
DPRejectB,
DPData, -- 32 bits
KBus,
-- 32 bits
-- Phase-multiplexed on KBus
aAdr [0..7]
bAdr [8..15]
cAdr [16..23]
EUSt3AisCBus2BA [24]
EUAluLeftSrc1BA [25..26]
EUAluRightSrc1BA [27..29]
EUStore2ASrc1BA [30..31]
EURdFromPBus3AB, EUWriteToPBus3AB,
EUAluOp2AB, -- 4 bits Dragon.ALUOps
EUCondSel2AB, -- 4 bits Dragon.CondSelects
EUCondition2B,
DShA, DShB, DShRd, DShWt, DShIn, DShOut, DHold, DStAd: NAT ← LAST[NAT],
-- registers
reg: ARRAY PipeRange OF CARD ← ALL[0],
shRegA, shRegB: CARD ← 0, -- the data part of the DBus shift register
op, dStateAd: NAT ← 0, -- the remainder of the shift register
prevDShift, prevDExecute: Ports.Level ← X, -- the DShift clock is edge-triggered
-- a few bits of state
carryAB, carryBA: BOOL ← FALSE,
conditionBA: BOOL ← FALSE, -- needed during A to update carryAB
rejectBA: BOOL ← FALSE, -- a copy of DPRejectB stable during PhA
readPBusBA: BOOL ← FALSE, -- a copy of EURdFromPBus3AB stable during the next PhA
-- register file
ram: SEQUENCE size: NAT OF CARD
size: NAT ← nRegs,
ram: ARRAY [0..nRegs) OF CARD
];