EU2Sim.mesa
Copyright © 1985 by Xerox Corporation. All rights reversed.
Created by Bertrand Serlet July 31, 1985 3:03:17 pm PDT
Last edited by Bertrand Serlet October 2, 1986 9:19:42 pm PDT
Barth, September 26, 1986 2:59:10 pm PDT
Louis Monier June 19, 1986 11:54:42 pm PDT
Last Edited by: Louis Monier October 20, 1986 10:25:48 am PDT
Last Edited by: Gasbarro October 1, 1986 6:05:58 pm PDT
DIRECTORY
Core, CoreFlat, EU2Utils, Rope, Rosemary, RosemaryUser, Ports;
EU2Sim: CEDAR PROGRAM
IMPORTS CoreFlat, EU2Utils, Rosemary, RosemaryUser, Ports =
BEGIN OPEN Core, EU2Utils;
-- A test program for simulation with Rosemary
Vdd, Gnd, PadVdd, PadGnd, PhA, PhB, VRef,
DPRejectB, DPData,  -- 32 bits
KBus,    -- 32 bits
EURdFromPBus3AB, EUWriteToPBus3AB,
EUAluOp2AB,  -- 4 bits Dragon.ALUOps
EUCondSel2AB,  -- 4 bits Dragon.CondSelects
EUCondition2B,
DShA, DShB, DShRd, DShWt, DShIn, DShOut, DHold, DStAd: NAT;
allOnes: LONG CARDINALLOOPHOLE[LONG[-1]];
Initialize: PROC [public: Wire] = {
Vdd ← PortIndex[public, "Vdd"];
Gnd ← PortIndex[public, "Gnd"];
PadVdd ← PortIndex[public, "PadVdd"];
PadGnd ← PortIndex[public, "PadGnd"];
PhA ← PortIndex[public, "PhA"];
PhB ← PortIndex[public, "PhB"];
VRef ← PortIndex[public, "VRef"];
DPRejectB ← PortIndex[public, "DPRejectB"];
DPData ← PortIndex[public, "DPData"];
KBus ← PortIndex[public, "KBus"];
EURdFromPBus3AB ← PortIndex[public, "EURdFromPBus3AB"];
EUWriteToPBus3AB ← PortIndex[public, "EUWriteToPBus3AB"];
EUAluOp2AB ← PortIndex[public, "EUAluOp2AB"];
EUCondSel2AB ← PortIndex[public, "EUCondSel2AB"];
EUCondition2B ← PortIndex[public, "EUCondition2B"];
DShA ← PortIndex[public, "DShA"];
DShB ← PortIndex[public, "DShB"];
DShRd ← PortIndex[public, "DShRd"];
DShWt ← PortIndex[public, "DShWt"];
DShIn ← PortIndex[public, "DShIn"];
DShOut ← PortIndex[public, "DShOut"];
DHold ← PortIndex[public, "DHold"];
DStAd ← PortIndex[public, "DStAd"];
[] ← Rosemary.SetFixedWire[public[Vdd], H];
[] ← Rosemary.SetFixedWire[public[Gnd], L];
[] ← Rosemary.SetFixedWire[public[PadVdd], H];
[] ← Rosemary.SetFixedWire[public[PadGnd], L];
[] ← Rosemary.SetFixedWire[public[VRef], H];
[] ← Ports.InitTesterDrive[public[PhA], force];
[] ← Ports.InitTesterDrive[public[PhB], force];
[] ← Ports.InitTesterDrive[public[DPRejectB], force];
[] ← Ports.InitPort[public[DPData], lc];
[] ← Ports.InitTesterDrive[public[DPData], expect];
[] ← Ports.InitPort[public[KBus], lc];
[] ← Ports.InitTesterDrive[public[KBus], force];
[] ← Ports.InitTesterDrive[public[EURdFromPBus3AB], force];
[] ← Ports.InitTesterDrive[public[EUWriteToPBus3AB], force];
[] ← Ports.InitPort[public[EUAluOp2AB], c];
[] ← Ports.InitTesterDrive[public[EUAluOp2AB], force];
[] ← Ports.InitPort[public[EUCondSel2AB], c];
[] ← Ports.InitTesterDrive[public[EUCondSel2AB], force];
[] ← Ports.InitTesterDrive[public[EUCondition2B], expect];
[] ← Ports.InitTesterDrive[public[DShA], force];
[] ← Ports.InitTesterDrive[public[DShB], force];
[] ← Ports.InitTesterDrive[public[DShRd], force];
[] ← Ports.InitTesterDrive[public[DShWt], force];
[] ← Ports.InitTesterDrive[public[DShIn], force];
[] ← Ports.InitTesterDrive[public[DShOut], expect];
[] ← Ports.InitTesterDrive[public[DHold], force];
[] ← Ports.InitPort[public[DStAd], c];
[] ← Ports.InitTesterDrive[public[DStAd], force];
};
ExerciseRose: PUBLIC PROC [ct: CellType, cutSets: LIST OF Rope.ROPENIL] RETURNS [tester: RosemaryUser.Tester] = {
Initialize[ct.public];
-- If testing the cellType
tester ← RosemaryUser.TestProcedureViewer[
cellType: ct,
testButtons: LIST["Sanity Check"],
name: "EU2Test",
displayWires: RosemaryUser.DisplayPortLeafWires[ct],
cutSet: CoreFlat.CreateCutSet[cellTypes: cutSets],
steady: FALSE];
};
END.