Documentation: BooleDoc.tioga

Commands: Boole

Created by: Bertrand Serlet

Maintained by: Bertrand Serlet <Serlet.pa>

Documentation: BringDAToolsDoc.tioga

Keywords: Design automation, Bringover, DATools, DF Files, DAToolsAdministration

Commands: BringDATools

Abstract: BringDATools is a command that brings over all the released DATools software in much less time that traditional bringovers.

Commands: Cabbage

Commands: CDBackgroundCheck

Commands: CDCifGen

Documentation: CMosLayersDoc.tioga

Commands: CDCMosA, CDNewCMosA, CMosA8BitColors, CDReadCMCMos

Documentation: CMosBLayersDoc.tioga

Commands: CDCMosB, CDNewCMosB, CMosB8BitColors

Commands: CDOpen, CDRead, ChipNDale, CDLoadCDBusCells

Documentation: CDConvertTechnologiesDoc.tioga

Commands: CDCount

Documentation: ChipNDaleIntroduction.tioga, ChipNDaleDoc.tioga, ChipNDaleToolsDoc.tioga, ChipNDaleProgramsDoc.tioga, CDCrib.tioga

Documentation: CDExtrasDoc.tioga, CDFeatureCheckDoc.tioga

Commands: CDUtil, CDDynamicObs, CDBottomUp, CDPropertyExtraction, CDColor, CDArrays, CDSimplifyStructure, CDSetDisplayTresholds

Commands: CDInterpress

Commands: CDLabel

Commands: CDNMosA, CDNewNMosA, CDCMNmosA, CDReadCMNMosA, NMosA8BitColors

Commands: CDPDPlot

Documentation: CDSatellitesDoc.tioga

Commands: CDSatellites

Documentation: LogicDoc.Tioga, StdCellsCmosBDoc.tioga

Commands: CellLibraries, SCCmosb

Documentation: ColorMapsDoc.tioga

Commands: ColorMaps

Created by: Bertrand Serlet, Mike Spreitzer and Rick Barth

Maintained by: Barth <Barth.pa>, Serlet <Serlet.pa>, Spreitzer <Spreitzer.pa>

Documentation: CoreDoc.tioga

Keywords: ChipNDale, Design Automation, Tools Integration

Commands: Core

Abstract: Core is a common set of interfaces for exchanging information between different DA tools. It is also used to capture the designer's intents at a high level.

Created by: Giordano Beretta

Documentation: CoreViewDoc.Tioga

Keywords: Core, Debugging, Design Automation Tools, Extraction, Illustration, Layout Visualization, Technology Independence, Viewers

Commands: CoreView

Abstract: CoreView visualizes the geometry in a Core data structure. Two options are available. With the first option a Core cell is recursively traversed and its geometry is painted into a viewer. The same non-linear RGB model as in Nectarine is used, hence the Cedar color map should be used. The second option simply creates an empty viewer, into which rectangles can be added incrementally. Viewers created with the second option are monochrome, every rectangle is labelled. This second option is intended for debugging packages based on Core.

Commands: CStitching

Documentation: DAUserDoc.tioga, DAToolsCatalog.tioga

Commands: DAUser, LayoutSimulation, LayoutSchematics, Schematics

Created by: Pradeep Sindhu as NewCoreClasses

Maintained by: Christian Le Cocq <LeCocq.pa>

Documentation: ElectricalCoreClassesDoc.tioga

Keywords: Circuit Simulation, Schematics Extraction

Abstract: ElectricalCoreClasses contains the definitions of the basic elements used in the electrical description of the circuits. It more or less follows the description understood by Spice.

Commands: ExtendCells

Documentation: ExtractDoc.tioga, SisyphDoc.tioga

Commands: Extract

Created by: Giordano Bruno Beretta

Documentation: GenistaDoc.Tioga

Keywords: Core, Design Rule Checking, Layout Verification, Design Automation Tools, Technology Independence

Commands: Genista, Drc, DrcCdCMOSb, DrcCMOSb

Abstract: Genista is the Grandson of Spinifex. It is a hierarchical design rule checker that enumerates a Core design and uses the ChipNDale geometry with which it is decorated to verify separation and width design rules. Clients can define enumeration procedures for own classes.

Documentation: GismoDoc.tioga

Commands: Gismo

Created by: Sweetsun Chen

Maintained by: Sweetsun Chen <SChen.pa>

Documentation: GraphDoc.tioga

Keywords: Graph, Controller, Thyme, Post Processor.

Commands: Graph, Waves

Abstract: Graph is a tool for creating or editing line graphs (x-y charts) manually or programmably. Many convenient functionalities are supported. The first section below contains tutorial steps to help users get familiar with the package easily.

Commands: ICTest, ICTestLocal

Commands: IMSTester, IMSTesterLocal

Commands: IMSLink

Documentation: MintDoc.tioga

Commands: Mint

Documentation: NectarineDoc.tioga

Commands: Nectarine, NectarineBoard, NectarineHybrid, NectarineLayout, NectarineSchematics, NectarineVanilla

Documentation: CoreThymeDoc.tioga, ThymeDoc.tioga, ThymeManual.tioga

Commands: Thyme

Created by: The Will of Rosemary's Users, who was obeyed by Rick Barth and Christian Le Cocq.

Maintained by: Christian Le Cocq <LeCocq.PA>

Documentation: PlotGraphDoc.tioga

Keywords: Viewers, Imager, InterPress, oscilloscope, Rosemary.

Commands: PlotGraph

Abstract: PlotGraph is a display package which provides the ability to show a collection of axis (i.e. display frames) layed out bottom up. Each axis is the local reference for one or more graphs (i.e. visualization of a set of data). The graphs can be displayed as curves, or the values can be written along the horizontal direction either horizontally or vertically.

Documentation: PWDoc.tioga

Commands: PW

Documentation: PWCoreDoc.tioga

Commands: PWCore

Commands: PWCoreLichen

Documentation: PWCoreRouteDoc.tioga

Commands: PWCoreRoute, PadFrame

Commands: PWRoute

Created by: Rick Barth

Maintained by: Barth <Barth.pa>

Documentation: RosemaryDoc.tioga, RosemaryExample.tioga, RosemaryTemplate.tioga

Keywords: Simulation

Commands: Rosemary

Abstract: Rosemary is a simulator.

Documentation: RouteAttributes.tioga

Commands: Route

Documentation: SCThingsToDo.tioga

Commands: SC, SCDAUser

Created by: Rick Barth

Maintained by: Barth <Barth.pa>

Documentation: ScaldDoc.tioga

Keywords: scald, file format

Commands: Scald

Abstract: Scald writes scald format files.

Created by: Christian Le Cocq

Maintained by: Christian Le Cocq <LeCocq.pa>

Documentation: SpiceOpsDoc.tioga, SpiceUserGuide.tioga

Keywords: Circuit Simulation, Schematics Extraction,

Commands: SpiceOps

Abstract: SpiceOps provides (as much as possible) simple ways to use the Spice Circuit simulator on the Vax in the Unix environment from our DATools in the Cedar environment.

Created by: Shand & Beretta

Maintained by: Giordano Beretta <Beretta.PA>

Documentation: SXConversion24.tioga, Spinifex24Doc.Tioga, CMosRules.tioga

Keywords: Corner-Based DRC, Design Automation Tools, Design Rule Checking, Extraction, Layout Verification, Level-Order Conflict Resolution, Technology Independence

Commands: Spinifex, CMosASpinifex, CMosBSpinifex, NMosASpinifex

Abstract: Spinifex is a circuit extractor and design rule checker. It features a new approach to the processing of hierarchically defined VLSI artwork, called level-order conflict resolution. The approach has the attractive features of retaining the cell hierarchy specified by the designer, and being applicable to the task of combined circuit extraction and geometric rule checking. Spinifex operates on constrained layouts and provides incremental analysis. The DRC part is corner-based.

Documentation: StaticDoc.tioga

Commands: Static

Documentation: IntHashTableThreadedDoc.tioga

Documentation: TerminalIODoc.tioga

Commands: TerminalIO

Documentation: WriteCapaDoc.tioga

Commands: WriteCapa