Created by: Bertrand Serlet

Maintained by: Bertrand Serlet <Serlet.pa>

Documentation: BooleDoc.tioga

Keywords: Boolean Algebra, Boolean expressions, Disjunctive Normal Form, PLA, DCVS, Cascode, Static

Commands: Boole

Abstract: Boole (also called Alps) is a layout generator which accepts a set of boolean equations, much like PLA generators do. It makes use of an original tree-structured representation of arbitrary boolean expressions. This representation is usually more compact than the classic disjunctive form, is suitable for fast symbolic manipulation, and maps naturally into silicon. Boole produces static CMOS layout using the cascode switch style.

Commands: LoadBringDATools, BringDATools24, BringDATools23

Commands: Cabbage

Commands: CDBackgroundCheck

Commands: CDCifGen

Documentation: CMosLayersDoc.tioga

Commands: CDCMosA, CDNewCMosA, CMosA8BitColors, CDReadCMCMos

Documentation: CMosBLayersDoc.tioga

Commands: CDCMosB, CDNewCMosB, CMosB8BitColors

Commands: ChipNDale, CDRead, CDOpen, CDLoadCDBusCells, CDOldPolygons, CDOldCDMenus

Documentation: CDConvertTechnologiesDoc.tioga

Documentation: ChipNDaleIntroduction.tioga, ChipNDaleDoc.tioga, ChipNDaleToolsDoc.tioga, ChipNDaleProgramsDoc.tioga, CDCrib.tioga

Documentation: CDExtrasDoc.tioga, CDFeatureCheckDoc.tioga

Commands: CDUtil, CDDynamicObs, CDBottomUp, CDPropertyExtraction, CDSimplifyStructure, CDSetDisplayTresholds, CDColor, CDArrays

Commands: CDLabel

Commands: CDMakeProc

Commands: CDNMos, CDNewNMos, CDCMNmos, CDReadCMNMos, NMos8BitColors

Commands: CDPDPlot

Documentation: CDSatellitesDoc.tioga

Commands: CDSatellites

Documentation: LogicDoc.Tioga, StdCellsCmosBDoc.tioga

Commands: CellLibraries

Created by: Giordano Beretta, Lissy Bland, Christian Jacobi

Maintained by: <Beretta.pa>

Documentation: ChipNSil23Doc.tioga

Keywords: ChipNDale, Documentation, Schematics, Illustration, Illustrator, Sil

Commands: CDSil, CDSilBW, ChipNSil, CDNewSil, CDReadSil, CDSil8BitColors

Abstract: ChipNSil is a graphical editor featuring the same user interface as ChipNDale. From an implementation point of view, ChipNSil is just another ChipNDale technology, therefore the designer needs no additional documentation beyond the ChipNDale documentation. However, ChipNSil is also used to create simple illustrations, and the ability to read Alto and Cedar Sil files has attracted users outside the designer community. This document shall help them to get started; it does not duplicate the full ChipNDale documentation.

Documentation: ColorMapsDoc.tioga

Commands: ColorMap

Created by: Bertrand Serlet, Mike Spreitzer and Rick Barth

Maintained by: Barth <Barth.pa>, Serlet <Serlet.pa>, Spreitzer <Spreitzer.pa>

Documentation: CoreDoc.tioga

Keywords: ChipNDale, Design Automation, Tools Integration

Commands: Core

Abstract: Core is a common set of interfaces for exchanging information between different DA tools. It is also used to capture the designer's intents at a high level.

Created by: Pradeep Sindhu

Maintained by: Sindhu <Sindhu.pa>

Documentation: CoreThymeDoc.tioga

Keywords: Circuit Simulation, Schematics Extraction

Commands: CoreThyme

Abstract: CORETHYME is a program that translates Core data structures into THYME input, permitting circuit diagrams drawn as schematics to be simulated conveniently. With some additional work it will also be possible to simulate layouts with comparable ease.

Commands: CStitching

Created by: Bertrand Serlet

Maintained by: Serlet <Serlet.pa>

Documentation: DAUserDoc.tioga, DAToolsCatalog.tioga

Keywords: Design automation, Core, ChipNDale, DATools, Bringover, Version Maps, Schematics, Simulation, Catalog, DF Files, BringDAUser

Commands: DAUser, BringDAUser, LayoutSimulation, LayoutSchematics, Schematics

Abstract: DAUser is a repository for commands, documentation or programs which are at the crossroads of different tools. DAUser contains the DATools catalog. DAUser also supplies the BringDAUser command, that allows fast recovery of all the DA sostware.

Created by: Bertrand Serlet

Maintained by: Serlet <Serlet.pa>, Frailong <Frailong.pa>, Sindhu <Sindhu.pa>

Documentation: ExtractDoc.tioga, SisyphDoc.tioga

Keywords: Layout Extractor, Schematics Extractor, Extraction, Technology Independent Extraction, Core, ChipNDale, Schematics, Wire Icons, Icons, Visual Programming, Schematics

Commands: Extract

Abstract: Extract is a package grouping the extraction engine [Sinix], the layout extractor and the schematics extractor [Sisyph].

Created by: Giordano Beretta & Christian Jacobi

Maintained by: Giordano Beretta <Beretta.PA>

Documentation: GismoDoc.tioga

Keywords: Design Rule Checking, Layout Verification, Design Automation Tools

Commands: Gismo

Abstract: Gismo is a collection of small interactive design rule checkers verifying single rules. Use the load file Gismo.Load and use the ChipNDale program menu to apply them interactively.

Created by: Sweetsun Chen

Maintained by: Sweetsun Chen <SChen.pa>

Documentation: GraphDoc.tioga

Keywords: Graph, Controller, Thyme, Post Processor.

Commands: Graph, Waves

Abstract: Graph is a tool for creating or editing line graphs (x-y charts) manually or programmably. Many convenient functionalities are supported. The first section below contains tutorial steps to help users get familiar with the package easily.

Commands: ICTest, ICTestLocal

Commands: IMSTester, IMSTesterLocal

Commands: IMSLink

Created by: Christian Le Cocq

Maintained by: Le Cocq <LeCocq.pa>

Documentation: MintDoc.tioga

Keywords: Circuit Simulation, Graph Display

Commands: Mint

Abstract: Mint is a program that simulates a Core data structure extracted from a layout.

Created by: Giordano Bruno Beretta

Maintained by: Giordano Bruno Beretta <Beretta.pa>

Documentation: NectarineDoc.tioga

Keywords: ChipNDale, ChipNSil, Documentation, Illustration, Imaging, Interpress, Layout Printing, No Fuzz, PD Files, Peach Expansion, Peach Printing, Printing, Schematics Printing, Sweet Dreams, Tioga Illustration

Commands: Nectarine, NectarineBoard, NectarineHybrid, NectarineSchematics

Abstract: The ultimate layout and schematics documentation and printing system. Creates Interpress masters and does with them anything you might dream of: stuffs into Tioga documents, prints on Interpress servers and Peach servers, in black and white or in colour, expanding on the printer server or on a special expansion server. Once three buttons are bugged to answer three orthogonal questions (what, where, how often), all the magic happens with the single press of a button. The Interpress masters can be further manipulated with Gargoyle.

Created by: Bertrand Serlet

Maintained by: Bertrand Serlet <Serlet.pa>

Documentation: OnionCoreDoc.tioga

Keywords: Routing, PadFrame, Loop Routing Scheme

Commands: OnionCore

Abstract: Onion is a small and (relatively) efficient PadRing router implemented from a paper by Smith, Saxe, Newkirk and Mathews (Stanford; CH1813-5, 1982 IEEE). This method is called Loop Routing Scheme (LRS).

Created by: The Will of Rosemary's Users, who was obeyed by Rick Barth and Christian Le Cocq.

Maintained by: Christian Le Cocq <LeCocq.PA>

Documentation: PlotGraphDoc.tioga

Keywords: Viewers, Imager, InterPress, oscilloscope, Rosemary.

Commands: PlotGraph

Abstract: PlotGraph is a display package which provides the ability to show a collection of axis (i.e. display frames) layed out bottom up. Each axis is the local reference for one or more graphs (i.e. visualization of a set of data). The graphs can be displayed as curves, or the values can be written along the horizontal direction either horizontally or vertically.

Created by: Louis Monier and Bertrand Serlet

Maintained by: Serlet <Serlet.pa>, Monier <Monier.pa>

Documentation: PWDoc.tioga

Keywords: BringOver, Layout Assembly, Layout Generator, Satellites, Silicon Assembly

Commands: PW

Abstract: PatchWork is a Silicon Assembler, i.e. a VLSI layout program which generates geometry from ChipNDale cells (usually hand-drawn) and a Cedar Program describing the topological placement of these cells. It runs under Cedar and is fully integrated in ChipNDale. This manual corresponds to the version ChipNDale 23. PatchWork is also a repository for other ChipNDale related conveniences, such as Satellites, or the BringOver command. Documentation for Satellites is in CDSatellitesDoc.tioga.

Created by: Bertrand Serlet, Louis Monier

Maintained by: Serlet <Serlet.pa>

Documentation: PWCoreDoc.tioga

Keywords: Comparator, Core, ChipNDale, PatchWork, Extraction, Sinix, Decorations, Interface Geometry

Commands: PWCore

Abstract: PWCore is the general framework for connecting CD layout to Core. The Core structure either comes from schematics, or by a piece of code. In both cases, this Core data structure is decorated with some properties, which permit the construction of the corresponding layout. When the layout is constructed, publics of cells having layout are decorated with the interface geometry, to allow for routing. A primitive interface check is made at that time, but no structural isomorphism is made at this point.

Commands: PWCoreLichen

Created by: Bertrand Serlet, Louis Monier, Bryan Preas

Maintained by: Bertrand Serlet <Serlet.pa>

Documentation: PWCoreRouteDoc.tioga

Keywords: Router, Pad Frame Generator, PWCore, Onion, Tools Integration

Commands: PWCoreRoute, PadFrame

Abstract: PWCoreRoute allows interfacing purely geometric routers to the world of structure. PWCoreRoute does not route in itself but calls routers within the framework define by PWCore. Currently PWCoreRoute proposes a Channel router and a PadFrame generator.

Created by: Bertrand Serlet

Maintained by: Serlet <Serlet.pa>

Documentation: PWDemoDoc.tioga

Commands: PWDemo

Abstract: PWDemo is a package for a flashing demo about the ChipNDale graphic editor, the PatchWork generator system and the Onion router. This demo represents the June 86 state of the tools and do not show any Core related tools.

Created by: Louis Monier

Maintained by: Serlet <Serlet.pa>, Monier <Monier.pa>

Documentation: PWPLADoc.tioga

Commands: PWPLA

Abstract: PWPLA is a PLA generator. It uses a library of cells, a set of user-defined parameters including a truth-table, and generates PLAs with the help of PatchWork. It can be used interactively from ChipnDale. Its procedural interface make it also easy to call from any user program.

Commands: PWRoute

Created by: Rick Barth

Maintained by: Barth <Barth.pa>

Documentation: RosemaryDoc.tioga

Keywords: Simulation

Commands: Rosemary

Abstract: Rosemary is a simulator.

Documentation: RouteAttributes.tioga

Commands: Route

Documentation: SCThingsToDo.tioga

Commands: SC

Created by: Rick Barth

Maintained by: Barth <Barth.pa>

Documentation: ScaldDoc.tioga

Keywords: scald, file format

Commands: Scald

Abstract: Scald writes scald format files.

Created by: Giordano Bruno Beretta

Documentation: SoSDoc.tioga

Keywords: Core, Design Rule Checking, Layout Verification, Design Automation Tools

Commands: SoS

Abstract: SoS is the Son of Spinifex. It is a hierarchical design rule checker that enumerates a Core design and uses the ChipNDale geometry with which it is decorated to verify separation and width design rules. Clients can define enumeration procedures for own classes.

Created by: Shand & Beretta

Maintained by: Giordano Beretta <Beretta.PA>

Documentation: Spinifex23Doc.Tioga, CMosRules.tioga

Keywords: Corner-Based DRC, Design Automation Tools, Design Rule Checking, Extraction, Layout Verification, Level-Order Conflict Resolution

Commands: Spinifex, CMosASpinifex, CMosBSpinifex, NMosSpinifex

Abstract: Spinifex is a circuit extractor and design rule checker. It features a new approach to the processing of hierarchically defined VLSI artwork, called level-order conflict resolution. The approach has the attractive features of retaining the cell hierarchy specified by the designer, and being applicable to the task of combined circuit extraction and geometric rule checking. Spinifex operates on constrained layouts and provides incremental analysis. The DRC part is corner-based.

Created by: Rick Barth

Maintained by: Barth <Barth.pa>

Documentation: StaticDoc.tioga

Keywords: design automation, static checking

Commands: Static

Abstract: Static checks that some interesting invariants hold.

Documentation: IntHashTableThreadedDoc.tioga

Documentation: TerminalIODoc.tioga

Commands: TerminalIO

Created by: Neil Welhelm

Maintained by: SChen.pa & DAToolsImplementors^.pa

Documentation: ThymeDoc.tioga, ThymeManual.tioga

Keywords: Circuit Simulation, Graph, Timing Diagrams.

Commands: Thyme

Abstract: Thyme is a circuit simulator originally written in the Alto environment in 1982, and ported to Cedar in 1984. This documentation only dicusses the special features of its Cedar version.

Created by: Christian Le Cocq

Maintained by: Christian Le Cocq <LeCocq.PA>

Documentation: WriteCapaDoc.tioga

Keywords: Capacitance, Layout, Core Wire

Commands: WriteCapa

Abstract: WriteCapa writes the capacitances of the layout wires as properties on the CoreWires