DIRECTORYGlobals,Rope;Model: CEDAR DEFINITIONS =BEGINOPEN Globals;ModelCmd: CmdProc;ParmCmd: CmdProc;TransistorCmd: CmdProc;NameToIndex: PROC[name: Rope.ROPE] RETURNS [index: INT];Delay: DelayProc;DelayProc: TYPE = PROC[stage: Stage, globalVars: GlobalVars];maxFetTypes: INTEGER = 32;diffCPerArea, polyCPerArea, metalCPerArea: REF REAL;diffCPerPerim: REF REAL;diffR, polyR, metalR: REF REAL;vdd, vinv: REF REAL;maxSlopePoints:  INTEGER = 10;  -- Size of slope tables.ParmArray: TYPE = ARRAY[0..maxSlopePoints) OF REAL;TType: TYPE = REF TTypeRec;TTypeRec: TYPE = RECORD [name: Rope.ROPE,strengthHi, strengthLo: INT,cPerArea, cPerWidth: REAL,rUp, rDown: REAL, on0, on1, onAlways: BOOLEAN,upESRatio, upREff, upOutES: REF ParmArray,downESRatio, downREff, downOutES: REF ParmArray];fetNEnh: INTEGER = 0;fetNEnhP: INTEGER = 1;fetNDep: INTEGER = 2;fetNLoad: INTEGER = 3;fetNSuper: INTEGER = 4;fetNChan: INTEGER = 5;fetPChan: INTEGER = 6;TypeTable:  ARRAY[0..maxFetTypes) OF TType;rUpFactor, rDownFactor: REF REAL;END.  þ  FILE: Model.mesaLast edited by Ousterhout, November 22, 1983 2:14 pmChristian LeCocq April 11, 1986 2:08:10 pm PSTThis file contains definitions related to the electrical models usedby Crystal.Processes the "model" command, used to see and set the current delay model.  If there is an argument, it is the name of the new model to use.Processes the "parameter" command, used to see and set the resistance and capacitance model parameters.  The arguments contain a sequence of parameter names and values. If no names are given, then the values of all parameters are printed out.Processes the "transistor" command.  If there are no arguments, then all fields of all transistor types are printed.  If there are arguments, the first one is the name of a transistor type, and subsequent arguments give <field value> pairs to set the individual fields for that transistor type.  If the transistor type isn't currently in the table, a new type is created.Given the name of a transistor type, this procedure returns its index in the type table.   Returns -1 if name isn't valid.Based on the information in stage and the time when its trigger changes (gotten from the previous stage) this routine calculates the delay through the stage and sets the settling time for the stage.Maximum number of different transistor types allowed:Resistance per square and capacitance per square micron on each of the mask layers:Voltages in the system.  Vdd is the supply voltage, Vinv is the logic threshold (delays and edge speeds are calculated at this voltage).Type records, defined below, are used to describe the various classes of transistor.  The idea is to make this information technology-independent enough to handle both nMOS and CMOS without any changes inside Crystal.  Certain types of transistor are predefined (see the list below).  The strength values indicate the relative pulling power of a transistor, and are used ony in logic simulation, to determine what wins when several fets tug at the same node. For example, loads have relatively low strength so they win only if there are no active drivers for a node.  The capacitance values are used in computing delays, as are the resistances, one used when the transistor is pulling up and one when it pulls down.Strength is only used during logic simulation.  It gives the relative pulling power of a transistor and is used to determine what wins when several fets tug at the same node.  For example, loads have relatively low strength so they win only if there are no active drivers for a node.Resistances are used in computing delays.  Each transistor type gets one characteristic resistance when it is pulling up, and one when it is pulling down.Miscellaneous flags:on0 means the transistor is turned on only when the gate is at logic 0.on1 means the transistor is turned on only when the gate is at logic 1.onAlways means the transistor is always turned on.  Exactly one of on0, on1, and onAlways should be set for any transistor type.The following arrays and values are used by the slope model in delay calculations.  See prSlopeImpl for details.Predefined transistor types are defined below.  NEnh and NDep are nMOS enhancement and depletion devices.  Transistors of type NLoad are nMOS depletion transistors with either source or drain connected to Vdd and the other terminal tied to the gate.  NSuper is used for NMOS depletion transistors with either source or drain connected to Vdd but the other terminal NOT tied to the gate. Types NChan and PChan are for n-channel and p-channel devices in CMOS.  Note that there are different types for n-channel enhancement devices in nMOS and CMOS.The following values are factors applied to parasitic resistances when computing delays.  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