DIRECTORY Core, CoreFlat, HashTable, IO, Rope; Globals: CEDAR DEFINITIONS = BEGIN Node: TYPE = REF NodeRec; NodeRec: TYPE = RECORD [ flatWire: CoreFlat.FlatWire, cap, res: REAL, hiTime, loTime: REAL, firstPointer: Pointer, always0, always1, input, output, bus, inPath, precharged, dynamic, watched, ratioError: BOOLEAN ]; Pointer: TYPE = REF PointerRec; PointerRec: TYPE = RECORD [ fet: Fet, next: Pointer ]; Fet: TYPE = REF FetRec; FetRec: TYPE = RECORD [ source, drain, gate: Node, area, aspect, x, y: REAL, type: INTEGER, flowFromSource, flowFromDrain, forcedOn, forcedOff, on0, on1, onAlways, noSourceInfo, noDrainInfo: BOOLEAN, firstFlow: FlowPtr ]; FlowCtl: TYPE = REF FlowRec; FlowRec: TYPE = RECORD [ name: Rope.ROPE, entered, left: Node, inOnly, outOnly, ignore, off: BOOLEAN ]; FlowPtr: TYPE = REF FlowPtrRec; FlowPtrRec: TYPE = RECORD [ flow: FlowCtl, next: FlowPtr, source, drain: BOOLEAN ]; pieceLimit: INT = 8; Stage: TYPE = REF StageRec; StageRec: TYPE = RECORD [ piece1Size, piece2Size: INT, time: REAL, edgeSpeed: REAL, rise: BOOLEAN, prev: Stage, piece1Fet, piece2Fet: ARRAY[0..pieceLimit) OF Fet, piece1Node, piece2Node: ARRAY[0..pieceLimit) OF Node ]; Arg: TYPE = REF ArgRec; ArgRec: TYPE = RECORD [ rope: Rope.ROPE, next: Arg ]; CmdProc: TYPE = PROC[args: Arg, globalVars: GlobalVars]; GlobalVars: TYPE = REF GlobalVarsRec; GlobalVarsRec: TYPE = RECORD[ rootCell: Core.CellType, VddNode, GroundNode: Node, nodeTable: HashTable.Table ]; RunCrystal: PROC [globalVars: GlobalVars]; StdOut: IO.STREAM; DupsOK: BOOLEAN; -- FALSE means avoid duplications in output. Stop: REF BOOLEAN; -- TRUE means user buttoned STOP! button. END. ¶FILE: Globals.mesa Last edited by Ousterhout, November 22, 1983 1:04 pm Christian LeCocq December 29, 1986 5:17:52 pm PST This file defines the circuit data structures manipulated by all of Crystal. There are three main elements in the data structure describing a circuit network. Objects of type Node correspond to the nets (a collection of things that are all electrically connected). Each Node contains some intrinsic resistance and capacitance, as well as pointers to the transistors that connect to it. The pointers are stored in a linked list of Pointer objects. The actual transistors are described in Fet objects. Each Fet contains pointers to the nodes it connects as well as information about the Fet, such as its type and shape. Note: all units in Crystal are as follows: Capacitance: pfs Resistance: ohms Time: ns Distance: microns Area: square microns name: Rope.ROPE, the only way to name a wire in the DATools world. Intrinsic capacitance and resistance. Worst-case rise and fall times seen for this node so far. Head of list of fets connnecting to this node. always0 means node has been determined always to be 0. always1 means node has been ddetermined always to be 1. input means node is forced to either 0 or 1 by outside world, but it's not known which (unless always0 or always1 is set) output means the value of the node is used by the outside world (this used in determining the signal flow) bus means the node is highly capacitive (used to chop up delay paths passing through the node) inPath is a piece of gingerbread left around when scanning depth-first through the circuit in order to prevent circular searches. precharged means node is set initially to 1, so consider only falling times. dynamic means node is a dynamic memory node. watched means delays to this node should be recorded in the special "watched" list. ratioError means a ratio violation has been found for the node. Nodes connecting to transistor. Location and shape of transistor: Type of transistor (index into type table). Various flags for transistors: flowFromSource means information can potentially flow through the fet from the source side. flowFromDrain means the same thing, except other side. forcedOn means the transistor has been determined through simulation always to be turned on. forcedOff means the transistor has been determined through simulation always to be turned off. on0, on1, and onalways are copies of the corresponding bits from the transistor's type. noSourceInfo means there is an "In" attribute attached to the transistor's drain or an "Out" attribute attached to its source. This flag prevents the flowFromSource flag from ever being set in the mark package. noDrainInfo means the same thing except for the transistor's drain. Pointer to first in list of flow records attached to this transistor. The following definitions are for data structures that are used to control information flow through complex transistor structures. Since a transistor may have several flow attributes attached to it, there are two different data structures. FlowCtls correspond to the controlling records, and FlowPtrs are used to link together all of the FlowCtls for a particular transistor. Entered is normally NIL. It is non-NIL if the current path requires information to enter the side of the transistor labelled with this attribute. In this case, entered refers to the node from which info flowed into this fet. Left has the same interpretation, except that it is non-NIL only when the current path requires information to leave the tagged side of the fet. These four flags are set by the "flow" command. InOnly means Crystal should never allow information to flow in to the transistor from the unnamed side. OutOnly means Crystal should never allow information to flow out from the unnamed side. Ignore means the flow attribute should be ignored completely, thereby permitting arbitrary flow with respect to this attribute. Out means Crystal should not allow any information flow through this transistor at all. Pointer to the flow record. Next pointer in chain of those attached to this transistor. Selects which transistor terminal the flow attribute is attached to. The following data structure is used to keep track of a single stage in a delay path. A stage is a path from a source of Vdd or Ground through transistor channels to a destination node (a gate or output). The delay module collects information about the transistors and nodes in the stage, then calls the model routines to compute the actual delay. Delay calculation for a stage is normally stimulated by a chnage in the value of a transistor gate somewhere along the stage. This transistor is called the trigger. Information about the stage is divided into two pieces: one piece between the trigger and Vdd or Ground, including the trigger (called piece1); and one piece between the trigger and the destination gate (called piece2). Each piece is limited in length to pieceLimit transistors in series. Within each piece, the fets and nodes are in order emanating out from the trigger. In piece1, node[i] is the one between fet[i] and fet[i+1], with the last node being the information source. In piece2, fet[i] is between node[i] and node[i+1]. The last node is the destination and the last fet in piece2 is NIL. Some stages don't have trigger transistors: examples are stages being driven by loads (the trigger is off to the side of the stage) and stages driven by an input or a bus through a pass transistor (the input or bus triggers the change, but there's no trigger transistor). In these cases, piece1Size is zero. Number of nodes in each piece. Time when stage finishes rising or falling. Slope of stage's waveform, in ns/volt. TRUE means stage rises, FALSE means it falls. Pointer to stage that triggers this stage, or NIL. The nodes and feets for each of the pieces. The data structure defined below is used to hold the arguments from a command line, in a linked list. Each rope contains one argument. An argument may either be a switch ("-" followed by a single character) or something else (anything not starting with a "-"). The following defines the command interpretation procedures. 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