[Cyan]<DATools6.1>CoreThyme>CoreThymeDoc.tioga!4

CoreThymeDoc.tioga

Written by: Pradeep Sindhu, April 3, 1986 6:10:44 pm PST

Last Edited by:

Bertrand Serlet July 9, 1986 12:28:19 pm PDT

Pradeep Sindhu, April 29, 1986 1:51:12 am PDT

CORETHYME: CIRCUIT SIMULATION WITHOUT TEARS

DATOOLS — FOR INTERNAL XEROX USE ONLY

CoreThyme: Circuit Simulation Without Tears

Pradeep Sindhu

User Manual

Release as [DATools]<DATools6.1>CoreThyme>CoreThymeDoc.tioga, .press

Abstract: CORETHYME is a program that translates Core data structures into THYME input, permitting circuit diagrams drawn as schematics to be simulated conveniently. With some additional work it will also be possible to simulate layouts with comparable ease.

Created by: Pradeep Sindhu

Maintained by: Sindhu <Sindhu.pa>

Keywords: Circuit Simulation, Schematics Extraction

XEROX Xerox Corporation
Palo Alto Research Center
3333 Coyote Hill Road
Palo Alto, California 94304

For Internal Xerox Use Only

Contents

Introduction

CORETHYME Icons

Programming Interface

User Interface

Running CORETHYME

Limitations

Introduction

Anyone who has prepared input for the circuit simulators THYME or SPICE by hand will concede that there are more convenient ways of accomplishing this task. The purpose of CORETHYME is to provide such a convenient method by translating Core data structures to THYME input. Since our new circuit extractors all output Core, schematics and layout may be simulated directly without having to deal with THYME's input language.

The input to CORETHYME is a Core cellType decorated with the information needed to run the THYME simulation. This cellType may have been produced using SISYPH, SinixCMosB, or for that matter constructed directly by program. For the purposes of this document, however, we will assume that the cellType has been obtained by drawing a schematic and extracting it using SISYPH. It is useful to recall that SISYPH schematics are drawn using icons that represent simpler schematics and wires that connect icons together. Icons may have arbitrary geometry, while wires are drawn as collections of connected rectangles (see the SISYPH documentation for more details).

To use CORETHYME, a user first draws his schematic using a mix of the the standard SSI icons and perhaps icons he has defined. He then adds a number of CORETHYME icons to provide signal drive, signal display, and simulation control. Finally, he encapsulates all of these in a ChipNDale cell and simulates it by pointing and clicking. Any parameters needed by THYME, as well as sizes of transistors and other components, etc. are specified in the standard way using satellites and/or expressions.

The remainder of this document provides details. The first section describes CORETHYME icons and how to use them. The following two sections cover the programming and user interfaces, while the last section describes how to run CORETHYME. It is assumed throughout that the reader is familiar with SISYPH and understands the essentials of Core.

CORETHYME Icons

CORETHYME provides a number of special icons that are useful in displaying values at selected nodes, driving selected nodes, and controlling the execution of THYME. These consist of circuit components, probes, signal generators, and the ThymePanel. A user gets these icons into his design by doing a CDBringOver of the library file EE.dale. The ThymePanel is special in that it must be included at the top level of the schematic to be simulated.

Circuit Components

These consist of the basic components Resistor, Inductor, and Capacitor. The default value of the resistor is 1 KOhm, but it may be modified by putting an instance satellite on the icon. For instance, the satellite R ← 0.01 sets the value to 10 Ohms (the units are in KOhms). The default value of the capacitor is 1.0pF, and the name of the capacitor variable is C (the units are pF). The default value of the inductor is 1.0mH, and the inductor variable is L (units are mH).

Probes

Probe icons are used to indicate that particular voltages or currents in the circuit should be plotted by THYME. There are two probe icons: VProbe, and IProbe.

VProbe is a one terminal device whose active terminal is attached to the node whose voltage is to be plotted (for the EE buffs, there is an implicit ground terminal internal to the probe's definition). VProbe takes one parameter, scale. Assigning to scale via an instance satellite causes the displayed voltage to be scaled by this factor (the default value of scale is 1.0).

IProbe is a two terminal device that is placed in series with the branch whose current is to be measured. In contrast with VProbe, IProbe results in putting a real component into the circuit to be simulated. This real component is either a 0 Volt voltage source or a resistor, depending on the value of the parameter R (for internal resistance). If R < 0.001KOhm then the component is a 0 Volt voltage source, otherwise it is an R KOhm resistor. IMeter also takes the parameter scale, which causes the displayed current to be scaled by this factor.

Signal Generators

Signal generator icons provide a way to drive circuit nodes with appropriate signals. There are four signal generators defined: Voltage, Step, Pulse, and RectWave.

The Voltage signal generator provides a source of DC voltage. The value of the voltage is set by the parameter onLevel with units Volts and default value 5.0.

The Step signal generator provides a step function. The low and high values of the step are set by the parameters offLevel and onLevel (both Volts, and default values 0.0 and 5.0). The step may be given a rise time, controlled by the parameter tRise (units nS, default value 5.0). The start of the step occurs at the time specified by the parameter tDelay (units nS, default value 10.0).

The Pulse signal generator provides a pulse function. The low and high values of the step are set by the parameters offLevel and onLevel (both Volts, and default values 0.0 and 5.0). The pulse may be given rise and fall times, controlled by the parameters tRise and tFall (units nS, default values 5.0). The start of the pulse occurs at the time specified by the parameter tDelay (units nS, default value 10.0), and its width is controlled by width (units nS, default 50.0). Note that the width of the pulse is from the instant the pulse departs from the offLevel to the instant it returns to this level.

The RectWave signal generator provides a periodic rectangular wave. The low and high values of the wave are set by the parameters offLevel and onLevel (both Volts, and default values 0.0 and 5.0). The wave may be given rise and fall times, controlled by the parameters tRise and tFall (units nS, default values 5.0). The start of the onLevel occurs at the time (within the period) specified by the parameter tDelay (units nS, default value 10.0), and its width is controlled by width (units nS, default 50.0). Note that the width of the on period is from the instant the pulse departs from the offLevel to the instant it returns to this level. The period is controlled by the parameter period (units nS, default 100.0).

Thyme Panel

The ThymePanel icon allows the user to control certain global simulation parameters. These include the graph title, the simulation start time, the simulation stop time, and the scales on the vertical and horizontal axes. It is mandatory to include a ThymePanel inside the top level cell to be simulated.

Programming Interface

The programming interface resides in CoreThyme.mesa. It defines three procedures.

InitThyme: PROC [wDir: ROPE] RETURNS [handle: ThymeHandle];

Initializes Thyme.

Translate: PROC [cellType: CellType, outputFile: ROPE];

Translates cellType into a Thyme file and puts the result in outputFile.

Simulate: PROC [inputFile: ROPE, handle: ThymeHandle];

Simulates the circuit specified in inputFile.

User Interface

The user interface for CORETHYME consists of one command called SISYPH Extract and THYME, available via the <space>-O menu. This command takes a selected ChipNDale cell as argument, extracts the cell using SISYPH, translates the resulting cellType into a THYME file and then invokes THYME on that file. The user of course never sees the file unless he explicitly opens it (I'd advise you against it!).

Running CORETHYME

1. Bringover -p [DATools]<DATools6.1>Top>DAUser.df

2. Type Schematics to the Commander.

3. Create a new CMosB design using CDNewCMosB.

4. Do a CDBringover of the file EE.dale (and SSI.dale if you want to draw SSI gates).

Limitations

CORETHYME does not as yet work on layout since we don't have a program to decorate the Core cellType for a layout with the stray capacitance from that layout. Once the decoration program is written it should be relatively straightforward to get CORETHYME to work on layout as well.