DIRECTORY CoreCreate; Logic: CEDAR DEFINITIONS = BEGIN OPEN CoreCreate; logicCutSet, macroCutSet: ROPE; -- used by Rosemary Inv: PROC RETURNS [ct: CellType]; Buffer: PROC[d: NAT] RETURNS [ct: CellType]; TstDriver: PROC RETURNS [ct: CellType]; TristateI: PROC RETURNS [ct: CellType]; TristateNI: PROC RETURNS [ct: CellType]; And: PROC[n: NAT] RETURNS [ct: CellType]; Nand: PROC[n: NAT] RETURNS [ct: CellType]; Or: PROC[n: NAT] RETURNS [ct: CellType]; Nor: PROC[n: NAT] RETURNS [ct: CellType]; Xor2: PROC RETURNS [ct: CellType]; Xnor2: PROC RETURNS [ct: CellType]; A22o2i: PROC RETURNS [ct: CellType]; O22a2i: PROC RETURNS [ct: CellType]; A21o2i: PROC RETURNS [ct: CellType]; FlipFlop: PROC RETURNS [ct: CellType]; FlipFlopEnable: PROC RETURNS [ct: CellType]; FlipFlopAsyncReset: PROC RETURNS [ct: CellType]; DLatch: PROC RETURNS [ct: CellType]; Storage: PROC RETURNS [ct: CellType]; RS: PROC RETURNS [ct: CellType]; MuxDN1: PROC [n: NAT] RETURNS [ct: CellType]; MuxD: PROC [n, b: NAT] RETURNS [ct: CellType]; MuxD2: PROC [b: NAT] RETURNS [ct: CellType]; MuxD4: PROC [b: NAT] RETURNS [ct: CellType]; MuxN1: PROC [n: NAT] RETURNS [ct: CellType]; Mux: PROC [n, b: NAT] RETURNS [ct: CellType]; Mux2: PROC [b: NAT] RETURNS [ct: CellType]; Mux4: PROC [b: NAT] RETURNS [ct: CellType]; TristateBuffer : PROC [b: NAT] RETURNS [ct: CellType]; TristateBufferInv : PROC [b: NAT] RETURNS [ct: CellType]; Adder: PROC [b: NAT] RETURNS [ct: CellType]; Constant: PROC [b: NAT, v: INT] RETURNS [ct: CellType]; Comparator: PROC [b: NAT] RETURNS [ct: CellType]; EqConstant: PROC [b: NAT, v: INT] RETURNS [ct: CellType]; DecoderS: PROC [a: NAT, s: NAT _ 0] RETURNS [ct: CellType]; Decoder: PROC [a: NAT, s: NAT _ 0] RETURNS [ct: CellType]; Register: PROC [b: NAT] RETURNS [ct: CellType]; RegisterR: PROC [b: NAT] RETURNS [ct: CellType]; RegisterSimple: PROC [b: NAT] RETURNS [ct: CellType]; CounterType: TYPE ~ {ripple, lookahead}; CounterUp: PROC [b: NAT, type: CounterType] RETURNS [ct: CellType]; ShRegLeft: PROC [b: NAT] RETURNS [ct: CellType]; Latch: PROC [b: NAT] RETURNS [ct: CellType]; Ram2: PROC [b, n: NAT] RETURNS [ct: CellType]; Fifo: PROC [b, n, nbFreeNF: NAT] RETURNS [ct: CellType]; Oracle: PROC [in, out, name: ROPE, log: BOOL _ FALSE] RETURNS [ct: CellType]; SetOracleFileName: PROC [id, fileName: ROPE]; GetOracleFileName: PROC [id: ROPE] RETURNS [fileName: ROPE]; WaveForm: PROC [val: ROPE, freq: NAT, firstEdge: INT] RETURNS [ct: CellType]; ClockGen: PROC [up, dn, firstEdge: INT, initLow: BOOL] RETURNS [ct: CellType]; Stop: PROC [] RETURNS [ct: CellType]; Counter: PROC [b: NAT] RETURNS [ct: CellType]; ShiftReg: PROC [b: NAT] RETURNS [ct: CellType]; FF2: PROC RETURNS [ct: CellType]; FF4: PROC RETURNS [ct: CellType]; END. ΄Logic.mesa Copyright c 1986 by Xerox Corporation. All rights reserved. Last Edited by: Louis Monier February 10, 1987 9:45:27 am PST Jean-Marc Frailong March 26, 1987 5:28:33 pm PST Pradeep Sindhu September 11, 1986 5:12:50 pm PDT -- This module provides the basic blocks for logic description and simulation of ICs. Every procedure corresponds to an icon in the library "Logic.dale"; extracting such an icon with Sisyph calls the corresponding procedure. The difference with a library like SSI is that there is no electrical notion attached to the cells, only logic behavior. -- There are two types of cells in this library: the simple ones and the composite ones. Simple ones (inverter, nor4, ...) are similar to the cells in SSI and correspond to a single standard cell in most decent libraries. The composite ones (i.e. adder, counter) have a Core structure using cells of the first type as leaves, or a very specific layout (RAM, ROM, PLA). All types have a behavioral procedure for logic simulation using Rosemary. -- CutSets for simulation -- Very basic standard cells "Vdd", "Gnd", "I", "X" "Vdd", "Gnd", "I", "X" "Vdd", "Gnd", "I", "X", "EN", "NEN" "Vdd", "Gnd", "I", "X", "EN" "Vdd", "Gnd", "I", "X", "EN" "Vdd", "Gnd", Seq["I", n] "X" "Vdd", "Gnd", Seq["I", n] "X" "Vdd", "Gnd", Seq["I", n] "X" "Vdd", "Gnd", Seq["I", n] "X" "Vdd", "Gnd", "I-A", "I-B", "X" "Vdd", "Gnd", "I-A", "I-B", "X" "Vdd", "Gnd", "A", "B", "C", "D" ,"X" "Vdd", "Gnd", "A", "B", "C", "D" ,"X" "Vdd", "Gnd", "A", "B", "C" ,"X" "Vdd", "Gnd", "D", "Q", "NQ", "CK" "Vdd", "Gnd", "D", "Q", "NQ", "CK", "en", "nEn" "Vdd", "Gnd", "D", "Q", "NQ", "CK", "r" "Vdd", "Gnd", "D", "Q", "S" -- Not standard cells, but basic cells anyway "Vdd", "Gnd", "bit", "nbit" "Vdd", "Gnd", "R", "S", "Q", "nQ" -- Multiplexers "Vdd", "Gnd", Seq["Select", n], Seq["In", n], "Output" "Vdd", "Gnd", Seq["Select", n], Seq["In", n, Seq[size: b]], Seq["Output", b] "Vdd", "Gnd", "Select0", "Select1", Seq["In0", b], Seq["In1", b], Seq["Output", b] "Vdd", "Gnd", "Select0", "Select1", "Select2", "Select3", Seq["In0", b], Seq["In1", b], Seq["In2", b], Seq["In3", b], Seq["Output", b] "Vdd", "Gnd", Seq["Select", s], Seq["In", n], "Output", with s=NbBits[n] "Vdd", "Gnd", Seq["Select", s], Seq["In", n, Seq[size: b]], Seq["Output", b] where s=NbBits[n] "Vdd", "Gnd", "Select", Seq["In0", b], Seq["In1", b], Seq["Output", b] "Vdd", "Gnd", Seq["Select", 2], Seq["In0", b], Seq["In1", b], Seq["In2", b], Seq["In3", b], Seq["Output", b] -- Buffers "Vdd", "Gnd", Seq["Input", b], Seq["Output", b], "enable" "Vdd", "Gnd", Seq["Input", b], Seq["Output", b], "enable" -- Arithmetic "Vdd", "Gnd", "carryIn", Seq["A", b], Seq["B", b], Seq["Sum", b], "carryOut" "Vdd", "Gnd", Seq["Output", b] Output is continuously driven to v with strength drive. "Vdd", "Gnd", Seq["A", b], Seq["B", b], "AEqB" "Vdd", "Gnd", Seq["In", b], "out" "Vdd", "Gnd", Seq["Address", a], Seq["Select", s], with s=0 => s _ 2**a "Vdd", "Gnd", Seq["Address", a], Seq["Select", s], "Enable", with s=0 => s _ 2**a -- Macros with states "Vdd", "Gnd", "CK", Seq["Input", b], Seq["Output", b], Seq["nOutput", b], "en" "Vdd", "Gnd", "CK", Seq["Input", b], Seq["Output", b], Seq["nOutput", b], "en", "r" "Vdd", "Gnd", "CK", Seq["Input", b], Seq["Output", b], Seq["nOutput", b] "Vdd", "Gnd", "Load", "Count", "Cin", "Cout", "CK", Seq["Input", b], Seq["Output", b], Seq["nOutput", b] Load has priority over Count. ripple means ripple carry counter (slow), lookahead means add lookahead logic (should reach 40MHz for 32 bits), best means use the fastest solution (ripple for very small counters, lookahead for large counters). "Vdd", "Gnd", "CK", "Load", "Shift", "inLSB", "outMSB", Seq["Input", b], Seq["Output", b], Seq["nOutput", b] Load has priority over Shift "Vdd", "Gnd", "CK", Seq["Input", b], Seq["Output", b] -- Standard generators "Vdd", "Gnd", Seq["Input", b], Seq["Output", b], Seq["RAdr", a], Seq["WAdr", a], "enW" For the custom block: "Vdd", "Gnd", "CK", Seq["Input", b], Seq["Output", b], "Read", "Write", "Reset" "Vdd", "Gnd", "CK", Seq["Input", b], Seq["Output", b], "Load", "UnLoad", "Reset", "DataAv", "Full", "NF" For the custom block: "Vdd", "Gnd", "CK", Seq["Input", b], Seq["Output", b], "Read", "Write", "Reset" -- For Rosemary simulation only (no layout) "In", "Out", "CK" "RosemaryLogicTime", "Out" Default values on icon: freq_2, firstEdge_1 "RosemaryLogicTime", "Clock" Default values on icon: up_dn_firstEdge_1; initLow_TRUE raises an error when its input "ShouldBeFalse" is true -- Avoid these: will be replaced some day "Vdd", "Gnd", "s0", "s1", "Cin", "Cout", "CK", Seq["Input", b], Seq["Output", b] s1=0, s0=0 => count down s1=0, s0=1 => count up s1=1, s0=0 => idle s1=1, s0=1 => load input "Vdd", "Gnd", "s0", "s1", "CK", "inL", "inR", Seq["Input", b], Seq["Output", b] s1=0, s0=0 => shift right s1=0, s0=1 => shift left s1=1, s0=0 => idle s1=1, s0=1 => load input "Vdd", "Gnd", "D0", "D1", "sel", "Q", "NQ", "CK" "Vdd", "Gnd", "D0", "D1", "D2", "D3", "s0", "s1", "s2", "CK", "Q", "NQ" Κ&˜codešœ ™ Kšœ Οmœ1™