<> <> <> <> <<>> <<-- Verifies every cell of the standard cell library SCLibCMOSB.dale, (2>> <<-- Compares the layout and schematics using Lichen.>> <<>> DIRECTORY CD, CDImports, Core, PW, Rope, Sisyph; TestStdCellsCmosB: CEDAR PROGRAM IMPORTS CDImports, PW, Sisyph ~ BEGIN <> <<-- The source of schematics and layout>> schDesignName: Rope.ROPE = "SCLibCMOSB"; schDesign: CD.Design; schDesignCx: Sisyph.Context; TestSCCell: PROC [schName: Rope.ROPE] ~ { <<-- PWCoreLichen.Compare[Sisyph.ExtractSchematicByName[name: schName, cx: schDesignCx]];>> [] _ Sisyph.ExtractSchematicByName[name: schName, cx: schDesignCx]; }; <> schDesign _ PW.OpenDesign[schDesignName]; [] _ CDImports.Load[into: schDesign, importeeName: "Logic"]; schDesignCx _ Sisyph.Create[schDesign]; <> <<>> TestSCCell["Feedthru.sch"]; TestSCCell["C2GD00A.sch"]; TestSCCell["C2VD00A.sch"]; TestSCCell["C2IV00A.sch"]; TestSCCell["C2IV00B.sch"]; TestSCCell["C2BD02A.sch"]; TestSCCell["C2AN02A.sch"]; TestSCCell["C2AN03A.sch"]; TestSCCell["C2AN04A.sch"]; TestSCCell["C2NA02A.sch"]; TestSCCell["C2NA03A.sch"]; TestSCCell["C2NA04A.sch"]; TestSCCell["C2OR02A.sch"]; TestSCCell["C2OR03A.sch"]; TestSCCell["C2OR04A.sch"]; TestSCCell["C2NO02A.sch"]; TestSCCell["C2NO03A.sch"]; TestSCCell["C2NO04A.sch"]; TestSCCell["C2XR02A.sch"]; TestSCCell["C2XN02A.sch"]; TestSCCell["a22o2i.sch"]; TestSCCell["o22a2i.sch"]; TestSCCell["a21o2i.sch"]; <> TestSCCell["ff.sch"]; TestSCCell["dLatch.sch"]; END.