MSI.mesa
Copyright © 1986 by Xerox Corporation. All rights reserved.
Barth, May 9, 1986 4:41:56 pm PDT
MSI: CEDAR DEFINITIONS = BEGIN OPEN CoreCreate;
Latch:
PROC
RETURNS [ct: CellType];
"Vdd", "Gnd", "Load", "Input", "Output"
Register:
PROC [b:
NAT]
RETURNS [ct: CellType];
"Vdd", "Gnd", "Load", Seq["Input", b], Seq["Output", b]
Constant:
PROC [b:
NAT, v:
INT]
RETURNS [ct: CellType];
"Vdd", "Gnd", Seq["Output", b]
Output is continuously driven to v with strength drive.
Multiplexor:
PROC [i:
NAT ← 2]
RETURNS [ct: CellType];
Seq["Select", i], Seq["Input", i], "Output"
BusMultiplexor:
PROC [b:
NAT, i:
NAT ← 2]
RETURNS [ct: CellType];
Seq["Select", i], Seq["Input", i, Seq[size: b]], Seq["Output", b]
Buffers:
PROC [b:
NAT]
RETURNS [ct: CellType];
"Vdd", "Gnd", Seq["Input", b], Seq["Output", b]
TristateBuffers:
PROC [b:
NAT]
RETURNS [ct: CellType];
"Vdd", "Gnd", "Drive", Seq["Input", b], Seq["Output", b]
Adder:
PROC [b:
NAT]
RETURNS [ct: CellType];
"Vdd", "Gnd", "CarryIn", Seq["A", b], Seq["B", b], Seq["Sum", b], "CarryOut"
Comparator:
PROC [b:
NAT]
RETURNS [ct: CellType];
"Vdd", "Gnd", Seq["A", i], Seq["B", i], "AEqB"
Decoder:
PROC [a:
NAT, s:
NAT ← 0]
RETURNS [ct: CellType];
"Vdd", "Gnd", Seq["Address", a], Seq["Select", s]
s=0 => s ← 2**a
ClockedDecoder:
PROC [a:
NAT, s:
NAT ← 0]
RETURNS [ct: CellType];
"Vdd", "Gnd", Seq["Address", a], Seq["Select", s], "Clock"
s=0 => s ← 2**a
s > 2**a => ERROR
ShiftRegister:
PROC [b:
NAT]
RETURNS [ct: CellType];
"Vdd", "Gnd", "ShiftA", "ShiftB", "Load", "LeftNRight", "LeftInput", "RightInput", Seq["Input", b], Seq["Output", b]
Counter:
PROC [b:
NAT]
RETURNS [ct: CellType];
"Vdd", "Gnd", "CountA", "CountB", "Load", "UpNDown", Seq["Input", b], Seq["Output", b]
RegisterFile:
PROC [b:
NAT, a:
NAT, w:
NAT ← 0]
RETURNS [ct: CellType];
"Vdd", "Gnd", "Load", Seq["Address", a], Seq["Input", b], Seq["Output", b]
w is the number of words
w=0 => w ← 2**a
w > 2**a => ERROR
MultiPortRegisterFile:
PROC [b:
NAT, a:
NAT, w:
NAT ← 0, rp:
NAT ← 1, wp:
NAT ← 1]
RETURNS [ct: CellType];
"Vdd", "Gnd", Seq["Load", wp], Seq["WriteAddress", wp, Seq[size: a]], Seq["ReadAddress", rp, Seq[size: a]], Seq["Input", wp, Seq[size: b]], Seq["Output", rp, Seq[size: b]]
w is the number of words
w=0 => w ← 2**a
w > 2**a => ERROR
END.