<> <> <> <> <> <<>> <<-- This module provides the basic blocks for logic description and simulation of ICs. Every procedure corresponds to an icon in the library "Logic.dale"; extracting such an icon with Sisyph calls the corresponding procedure. The difference with a library like SSI is that there is no electrical notion attached to the cells, only logic behavior.>> <<-- There are two types of cells in this library: the simple ones and the composite ones. Simple ones (inverter, nor4, ...) are similar to the cells in SSI and correspond to a single standard cell in most decent libraries. The composite ones (i.e. adder, counter) have a Core structure using cells of the first type as leaves, or a very specific layout (RAM, ROM, PLA). All types have a behavioral procedure for logic simulation using Rosemary.>> <<>> DIRECTORY CoreCreate; Logic: CEDAR DEFINITIONS = BEGIN OPEN CoreCreate; <<-- CutSets for simulation>> logicCutSet, macroCutSet: ROPE; -- used by Rosemary <<>> <<-- Very basic standard cells>> Inv: PROC RETURNS [ct: CellType]; <<"Vdd", "Gnd", "I", "X">> Buffer: PROC[d: NAT] RETURNS [ct: CellType]; <<"Vdd", "Gnd", "I", "X">> TstDriver: PROC RETURNS [ct: CellType]; <<"Vdd", "Gnd", "I", "X", "EN", "NEN">> TristateI: PROC RETURNS [ct: CellType]; <<"Vdd", "Gnd", "I", "X", "EN">> TristateNI: PROC RETURNS [ct: CellType]; <<"Vdd", "Gnd", "I", "X", "EN">> <<>> And: PROC[n: NAT] RETURNS [ct: CellType]; <<"Vdd", "Gnd", Seq["I", n] "X">> Nand: PROC[n: NAT] RETURNS [ct: CellType]; <<"Vdd", "Gnd", Seq["I", n] "X">> Or: PROC[n: NAT] RETURNS [ct: CellType]; <<"Vdd", "Gnd", Seq["I", n] "X">> Nor: PROC[n: NAT] RETURNS [ct: CellType]; <<"Vdd", "Gnd", Seq["I", n] "X">> Xor2: PROC RETURNS [ct: CellType]; <<"Vdd", "Gnd", "I-A", "I-B", "X">> Xnor2: PROC RETURNS [ct: CellType]; <<"Vdd", "Gnd", "I-A", "I-B", "X">> <<>> A22o2i: PROC RETURNS [ct: CellType]; <<"Vdd", "Gnd", "A", "B", "C", "D" ,"X">> O22a2i: PROC RETURNS [ct: CellType]; <<"Vdd", "Gnd", "A", "B", "C", "D" ,"X">> A21o2i: PROC RETURNS [ct: CellType]; <<"Vdd", "Gnd", "A", "B", "C" ,"X">> <<>> FlipFlop: PROC RETURNS [ct: CellType]; <<"Vdd", "Gnd", "D", "Q", "NQ", "CK">> FlipFlopEnable: PROC RETURNS [ct: CellType]; <<"Vdd", "Gnd", "D", "Q", "NQ", "CK", "en", "nEn">> FlipFlopAsyncReset: PROC RETURNS [ct: CellType]; <<"Vdd", "Gnd", "D", "Q", "NQ", "CK", "r">> DLatch: PROC RETURNS [ct: CellType]; <<"Vdd", "Gnd", "D", "Q", "S">> <<-- Not standard cells, but basic cells anyway>> Storage: PROC RETURNS [ct: CellType]; <<"Vdd", "Gnd", "bit", "nbit">> RS: PROC RETURNS [ct: CellType]; <<"Vdd", "Gnd", "R", "S", "Q", "nQ">> <<-- Multiplexers>> MuxDN1: PROC [n: NAT] RETURNS [ct: CellType]; <<"Vdd", "Gnd", Seq["Select", n], Seq["In", n], "Output">> MuxD: PROC [n, b: NAT] RETURNS [ct: CellType]; <<"Vdd", "Gnd", Seq["Select", n], Seq["In", n, Seq[size: b]], Seq["Output", b]>> MuxD2: PROC [b: NAT] RETURNS [ct: CellType]; <<"Vdd", "Gnd", "Select0", "Select1", Seq["In0", b], Seq["In1", b], Seq["Output", b]>> MuxD4: PROC [b: NAT] RETURNS [ct: CellType]; <<"Vdd", "Gnd", "Select0", "Select1", "Select2", "Select3", Seq["In0", b], Seq["In1", b], Seq["In2", b], Seq["In3", b], Seq["Output", b]>> MuxN1: PROC [n: NAT] RETURNS [ct: CellType]; <<"Vdd", "Gnd", Seq["Select", s], Seq["In", n], "Output", with s=NbBits[n]>> Mux: PROC [n, b: NAT] RETURNS [ct: CellType]; <<"Vdd", "Gnd", Seq["Select", s], Seq["In", n, Seq[size: b]], Seq["Output", b]>> <> Mux2: PROC [b: NAT] RETURNS [ct: CellType]; <<"Vdd", "Gnd", "Select", Seq["In0", b], Seq["In1", b], Seq["Output", b]>> Mux4: PROC [b: NAT] RETURNS [ct: CellType]; <<"Vdd", "Gnd", Seq["Select", 2], Seq["In0", b], Seq["In1", b], Seq["In2", b], Seq["In3", b], Seq["Output", b]>> <<>> <<-- Buffers>> TristateBuffer : PROC [b: NAT] RETURNS [ct: CellType]; <<"Vdd", "Gnd", Seq["Input", b], Seq["Output", b], "enable">> TristateBufferInv : PROC [b: NAT] RETURNS [ct: CellType]; <<"Vdd", "Gnd", Seq["Input", b], Seq["Output", b], "enable">> <<>> <<-- Arithmetic>> Adder: PROC [b: NAT] RETURNS [ct: CellType]; <<"Vdd", "Gnd", "carryIn", Seq["A", b], Seq["B", b], Seq["Sum", b], "carryOut">> Constant: PROC [b: NAT, v: INT] RETURNS [ct: CellType]; <<"Vdd", "Gnd", Seq["Output", b]>> <

> Comparator: PROC [b: NAT] RETURNS [ct: CellType]; <<"Vdd", "Gnd", Seq["A", b], Seq["B", b], "AEqB">> EqConstant: PROC [b: NAT, v: INT] RETURNS [ct: CellType]; <<"Vdd", "Gnd", Seq["In", b], "out">> DecoderS: PROC [a: NAT, s: NAT _ 0] RETURNS [ct: CellType]; <<"Vdd", "Gnd", Seq["Address", a], Seq["Select", s], with s=0 => s _ 2**a>> Decoder: PROC [a: NAT, s: NAT _ 0] RETURNS [ct: CellType]; <<"Vdd", "Gnd", Seq["Address", a], Seq["Select", s], "Enable", with s=0 => s _ 2**a>> <<>> <<-- Macros with states>> Register: PROC [b: NAT] RETURNS [ct: CellType]; <<"Vdd", "Gnd", "CK", Seq["Input", b], Seq["Output", b], Seq["nOutput", b], "en">> RegisterR: PROC [b: NAT] RETURNS [ct: CellType]; <<"Vdd", "Gnd", "CK", Seq["Input", b], Seq["Output", b], Seq["nOutput", b], "en", "r">> RegisterSimple: PROC [b: NAT] RETURNS [ct: CellType]; <<"Vdd", "Gnd", "CK", Seq["Input", b], Seq["Output", b], Seq["nOutput", b]>> CounterType: TYPE ~ {ripple, lookahead}; CounterUp: PROC [b: NAT, type: CounterType] RETURNS [ct: CellType]; <<"Vdd", "Gnd", "Load", "Count", "Cin", "Cout", "CK", Seq["Input", b], Seq["Output", b], Seq["nOutput", b]>> <> ShRegLeft: PROC [b: NAT] RETURNS [ct: CellType]; <<"Vdd", "Gnd", "CK", "Load", "Shift", "inLSB", "outMSB", Seq["Input", b], Seq["Output", b], Seq["nOutput", b]>> <> Latch: PROC [b: NAT] RETURNS [ct: CellType]; <<"Vdd", "Gnd", "CK", Seq["Input", b], Seq["Output", b]>> <<-- Standard generators>> Ram2: PROC [b, n: NAT] RETURNS [ct: CellType]; <<"Vdd", "Gnd", Seq["Input", b], Seq["Output", b], Seq["RAdr", a], Seq["WAdr", a], "enW">> <> Fifo: PROC [b, n, nbFreeNF: NAT] RETURNS [ct: CellType]; <<"Vdd", "Gnd", "CK", Seq["Input", b], Seq["Output", b], "Load", "UnLoad", "Reset", "DataAv", "Full", "NF">> <> <<>> <<-- For Rosemary simulation only (no layout)>> Oracle: PROC [in, out, name: ROPE, log: BOOL _ FALSE] RETURNS [ct: CellType]; <<"In", "Out", "CK">> SetOracleFileName: PROC [id, fileName: ROPE]; GetOracleFileName: PROC [id: ROPE] RETURNS [fileName: ROPE]; WaveForm: PROC [val: ROPE, freq: NAT, firstEdge: INT] RETURNS [ct: CellType]; <<"RosemaryLogicTime", "Out">> <> ClockGen: PROC [up, dn, firstEdge: INT, initLow: BOOL] RETURNS [ct: CellType]; <<"RosemaryLogicTime", "Clock">> <> Stop: PROC [] RETURNS [ct: CellType]; <> <<>> <<>> <<>> <<-- Avoid these: will be replaced some day>> Counter: PROC [b: NAT] RETURNS [ct: CellType]; <<"Vdd", "Gnd", "s0", "s1", "Cin", "Cout", "CK", Seq["Input", b], Seq["Output", b]>> < count down>> < count up>> < idle>> < load input>> ShiftReg: PROC [b: NAT] RETURNS [ct: CellType]; <<"Vdd", "Gnd", "s0", "s1", "CK", "inL", "inR", Seq["Input", b], Seq["Output", b]>> < shift right>> < shift left>> < idle>> < load input>> FF2: PROC RETURNS [ct: CellType]; <<"Vdd", "Gnd", "D0", "D1", "sel", "Q", "NQ", "CK">> FF4: PROC RETURNS [ct: CellType]; <<"Vdd", "Gnd", "D0", "D1", "D2", "D3", "s0", "s1", "s2", "CK", "Q", "NQ">> <<>> END.