DIRECTORY BitOps, Core, Ports, Rosemary, RosemaryUser; TestMSI: CEDAR PROGRAM IMPORTS BitOps, Ports, Rosemary, RosemaryUser = BEGIN Vdd: NAT; Gnd: NAT; PhA: NAT; PhB: NAT; AEqB: NAT; TriDrive: NAT; TriDriveIn: NAT; TriOut: NAT; RegOut: NAT; Select: NAT; ClockedSelect: NAT; BusMuxOut: NAT; MuxOut: NAT; AddA: NAT; AddB: NAT; COut: NAT; LoadShift: NAT; LeftShift: NAT; LeftIn: NAT; RightIn: NAT; ShiftOut: NAT; CounterLoad: NAT; CountUp: NAT; CounterOutput: NAT; RegisterLoad: NAT; RegisterAdr: NAT; RegisterOutput: NAT; MultiLoad: NAT; WriteAdr: NAT; ReadAdr: NAT; MultiInput: NAT; MultiOutput: NAT; Init: PROC [ct: Core.CellType] = { Vdd _ Ports.PortIndex[ct.public, "Vdd"]; Gnd _ Ports.PortIndex[ct.public, "Gnd"]; PhA _ Ports.PortIndex[ct.public, "PhA"]; PhB _ Ports.PortIndex[ct.public, "PhB"]; AEqB _ Ports.PortIndex[ct.public, "AEqB"]; TriDrive _ Ports.PortIndex[ct.public, "TriDrive"]; TriDriveIn _ Ports.PortIndex[ct.public, "TriDriveIn"]; TriOut _ Ports.PortIndex[ct.public, "TriOut"]; RegOut _ Ports.PortIndex[ct.public, "RegOut"]; Select _ Ports.PortIndex[ct.public, "Select"]; ClockedSelect _ Ports.PortIndex[ct.public, "ClockedSelect"]; BusMuxOut _ Ports.PortIndex[ct.public, "BusMuxOut"]; MuxOut _ Ports.PortIndex[ct.public, "MuxOut"]; AddA _ Ports.PortIndex[ct.public, "AddA"]; AddB _ Ports.PortIndex[ct.public, "AddB"]; COut _ Ports.PortIndex[ct.public, "COut"]; LoadShift _ Ports.PortIndex[ct.public, "LoadShift"]; LeftShift _ Ports.PortIndex[ct.public, "LeftShift"]; LeftIn _ Ports.PortIndex[ct.public, "LeftIn"]; RightIn _ Ports.PortIndex[ct.public, "RightIn"]; ShiftOut _ Ports.PortIndex[ct.public, "ShiftOut"]; CounterLoad _ Ports.PortIndex[ct.public, "CounterLoad"]; CountUp _ Ports.PortIndex[ct.public, "CountUp"]; CounterOutput _ Ports.PortIndex[ct.public, "CounterOutput"]; RegisterLoad _ Ports.PortIndex[ct.public, "RegisterLoad"]; RegisterAdr _ Ports.PortIndex[ct.public, "RegisterAdr"]; RegisterOutput _ Ports.PortIndex[ct.public, "RegisterOutput"]; MultiLoad _ Ports.PortIndex[ct.public, "MultiLoad"]; WriteAdr _ Ports.PortIndex[ct.public, "WriteAdr"]; ReadAdr _ Ports.PortIndex[ct.public, "ReadAdr"]; MultiInput _ Ports.PortIndex[ct.public, "MultiInput"]; MultiOutput _ Ports.PortIndex[ct.public, "MultiOutput"]; [] _ Rosemary.SetFixedWire[ct.public[Vdd], H]; [] _ Rosemary.SetFixedWire[ct.public[Gnd], L]; [] _ Ports.InitTesterDrive[wire: ct.public[PhA], initDrive: force]; [] _ Ports.InitTesterDrive[wire: ct.public[PhB], initDrive: force]; [] _ Ports.InitTesterDrive[wire: ct.public[TriDriveIn], initDrive: force]; [] _ Ports.InitTesterDrive[wire: ct.public[AddA], initDrive: force]; [] _ Ports.InitTesterDrive[wire: ct.public[AddB], initDrive: force]; [] _ Ports.InitTesterDrive[wire: ct.public[LoadShift], initDrive: force]; [] _ Ports.InitTesterDrive[wire: ct.public[LeftShift], initDrive: force]; [] _ Ports.InitTesterDrive[wire: ct.public[LeftIn], initDrive: force]; [] _ Ports.InitTesterDrive[wire: ct.public[RightIn], initDrive: force]; [] _ Ports.InitTesterDrive[wire: ct.public[CounterLoad], initDrive: force]; [] _ Ports.InitTesterDrive[wire: ct.public[CountUp], initDrive: force]; [] _ Ports.InitTesterDrive[wire: ct.public[RegisterLoad], initDrive: force]; [] _ Ports.InitTesterDrive[wire: ct.public[RegisterAdr], initDrive: force]; [] _ Ports.InitTesterDrive[wire: ct.public[MultiLoad][0], initDrive: force]; [] _ Ports.InitTesterDrive[wire: ct.public[WriteAdr][0][0], initDrive: force]; [] _ Ports.InitTesterDrive[wire: ct.public[WriteAdr][0][1], initDrive: force]; [] _ Ports.InitTesterDrive[wire: ct.public[ReadAdr][0][0], initDrive: force]; [] _ Ports.InitTesterDrive[wire: ct.public[ReadAdr][0][1], initDrive: force]; [] _ Ports.InitTesterDrive[wire: ct.public[ReadAdr][1][0], initDrive: force]; [] _ Ports.InitTesterDrive[wire: ct.public[ReadAdr][1][1], initDrive: force]; [] _ Ports.InitTesterDrive[wire: ct.public[MultiInput][0][0], initDrive: force]; [] _ RosemaryUser.TestProcedureViewer[name: "MSI Tester", cellType: ct, testButtons: LIST["TestMSI"], displayWires: RosemaryUser.DisplayPortLeafWires[ct]]; }; TestMSI: RosemaryUser.TestProc = { p[PhA].b _ FALSE; p[PhB].b _ FALSE; p[TriDriveIn].b _ TRUE; p[LoadShift].b _ TRUE; p[CounterLoad].b _ TRUE; p[RegisterLoad].b _ TRUE; p[MultiLoad][0].b _ TRUE; Eval[! Rosemary.Stop => IF data = $BoolWireHasX THEN RESUME ELSE REJECT]; p[LoadShift].b _ FALSE; p[CounterLoad].b _ FALSE; p[RegisterLoad].b _ FALSE; p[MultiLoad][0].b _ FALSE; p[PhA].b _ FALSE; p[PhB].b _ TRUE; Eval[! Rosemary.Stop => IF data = $BoolWireHasX THEN RESUME ELSE REJECT]; p[PhA].b _ TRUE; p[PhB].b _ FALSE; p[BusMuxOut].d _ expect; p[BusMuxOut].c _ 5; p[RegOut].d _ expect; p[ClockedSelect].d _ expect; p[Select].d _ expect; FOR b: NAT IN [0..16) DO p[AddB].c _ b; p[RegOut].c _ b; p[Select].c _ p[ClockedSelect].c _ BitOps.TwoToThe[15-b]; Eval[]; ENDLOOP; p[RegOut].d _ none; p[ClockedSelect].d _ none; p[Select].d _ none; p[TriOut].d _ expect; p[COut].d _ expect; p[AEqB].d _ expect; FOR a: NAT IN [0..16) DO FOR b: NAT IN [0..16) DO p[AddA].c _ a; p[AddB].c _ b; p[TriOut].c _ (a+b) MOD 16; p[COut].b _ (a+b) >= 16; p[AEqB].b _ a=b; Eval[]; ENDLOOP; ENDLOOP; p[COut].d _ none; p[AEqB].d _ none; p[TriDriveIn].b _ FALSE; FOR a: NAT IN [0..16) DO FOR b: NAT IN [0..16) DO p[AddA].c _ a; p[AddB].c _ b; Eval[]; ENDLOOP; ENDLOOP; p[TriOut].d _ none; p[PhA].b _ FALSE; p[BusMuxOut].d _ expect; p[MuxOut].d _ expect; p[TriDrive].d _ expect; p[TriDrive].b _ FALSE; p[RegOut].d _ expect; p[RegOut].c _ 15; p[ClockedSelect].d _ expect; p[ClockedSelect].c _ 0; FOR a: NAT IN [0..16) DO FOR b: NAT IN [0..16) DO p[AddA].c _ a; p[AddB].c _ b; p[BusMuxOut].c _ (a+b) MOD 16; p[TriDriveIn].b _ NOT p[TriDriveIn].b; p[MuxOut].b _ (a+b) >= 16; Eval[]; ENDLOOP; ENDLOOP; p[BusMuxOut].d _ none; p[MuxOut].d _ none; p[TriDrive].d _ none; p[RegOut].d _ none; p[ClockedSelect].d _ none; p[PhA].b _ FALSE; p[PhB].b _ FALSE; p[CounterOutput].d _ expect; p[ShiftOut].d _ expect; FOR b: NAT DECREASING IN [0..16) DO p[CounterLoad].b _ TRUE; p[LoadShift].b _ TRUE; p[AddB].c _ b; Eval[]; p[CounterLoad].b _ FALSE; p[LoadShift].b _ FALSE; Eval[]; p[PhB].b _ TRUE; p[CounterOutput].c _ b; p[ShiftOut].c _ b; Eval[]; p[PhB].b _ FALSE; Eval[]; ENDLOOP; p[CountUp].b _ TRUE; p[LeftShift].b _ TRUE; p[RightIn].b _ TRUE; FOR b: NAT IN [0..16) DO p[PhA].b _ TRUE; Eval[]; p[PhA].b _ FALSE; Eval[]; p[PhB].b _ TRUE; p[CounterOutput].c _ (b+1) MOD 16; IF b<4 THEN p[ShiftOut].c _ 2*p[ShiftOut].c+1; Eval[]; p[PhB].b _ FALSE; Eval[]; ENDLOOP; p[CountUp].b _ FALSE; p[LeftShift].b _ FALSE; p[LeftIn].b _ FALSE; FOR b: NAT DECREASING IN [0..16) DO p[PhA].b _ TRUE; Eval[]; p[PhA].b _ FALSE; Eval[]; p[PhB].b _ TRUE; p[CounterOutput].c _ b; p[ShiftOut].c _ p[ShiftOut].c/2; Eval[]; p[PhB].b _ FALSE; Eval[]; ENDLOOP; p[CounterOutput].d _ none; p[ShiftOut].d _ none; p[RegisterOutput].d _ expect; p[MultiOutput].d _ expect; p[RegisterLoad].b _ TRUE; p[MultiLoad][0].b _ TRUE; FOR b: NAT IN [0..4) DO p[RegisterAdr].c _ b; p[AddB].c _ b; p[RegisterOutput].c _ b; p[WriteAdr][0][0].b _ IF b>1 THEN TRUE ELSE FALSE; p[WriteAdr][0][1].b _ IF (b MOD 2) = 1 THEN TRUE ELSE FALSE; p[ReadAdr][0][0].b _ IF b>1 THEN TRUE ELSE FALSE; p[ReadAdr][0][1].b _ IF (b MOD 2) = 1 THEN TRUE ELSE FALSE; p[ReadAdr][1][0].b _ IF b>1 THEN TRUE ELSE FALSE; p[ReadAdr][1][1].b _ IF (b MOD 2) = 1 THEN TRUE ELSE FALSE; p[MultiInput][0][0].b _ IF (b MOD 2) = 1 THEN TRUE ELSE FALSE; p[MultiOutput][0][0].b _ IF (b MOD 2) = 1 THEN TRUE ELSE FALSE; p[MultiOutput][1][0].b _ IF (b MOD 2) = 1 THEN TRUE ELSE FALSE; Eval[]; ENDLOOP; p[RegisterLoad].b _ FALSE; p[MultiLoad][0].b _ FALSE; FOR b: NAT IN [0..4) DO p[RegisterAdr].c _ b; p[RegisterOutput].c _ b; p[ReadAdr][0][0].b _ IF b>1 THEN TRUE ELSE FALSE; p[ReadAdr][0][1].b _ IF (b MOD 2) = 1 THEN TRUE ELSE FALSE; p[ReadAdr][1][0].b _ IF b>1 THEN TRUE ELSE FALSE; p[ReadAdr][1][1].b _ IF (b MOD 2) = 1 THEN TRUE ELSE FALSE; p[MultiOutput][0][0].b _ IF (b MOD 2) = 1 THEN TRUE ELSE FALSE; p[MultiOutput][1][0].b _ IF (b MOD 2) = 1 THEN TRUE ELSE FALSE; Eval[]; ENDLOOP; }; RosemaryUser.RegisterTestProc["TestMSI", TestMSI]; END. vTestMSI.mesa Barth, October 10, 1986 5:36:32 pm PDT Last Edited by: Louis Monier August 7, 1986 8:14:01 pm PDT Κ β˜codešœ ™ K™&K™:—K˜KšΟk œ-˜6K˜šΟnœœ˜Kšœ(˜/Kš˜—K˜Kšœœ˜ Kšœœ˜ Kšœœ˜ Kšœœ˜ Kšœœ˜ Kšœ œ˜Kšœ œ˜Kšœœ˜ Kšœœ˜ Kšœœ˜ Kšœœ˜Kšœ œ˜Kšœœ˜ Kšœœ˜ Kšœœ˜ Kšœœ˜ Kšœ œ˜Kšœ œ˜Kšœœ˜ Kšœ œ˜ Kšœ œ˜Kšœ œ˜Kšœ œ˜ Kšœœ˜Kšœœ˜Kšœ œ˜Kšœœ˜Kšœ œ˜Kšœ œ˜Kšœ œ˜ Kšœ œ˜Kšœ œ˜K˜šžœœ˜"Kšœ(˜(Kšœ(˜(Kšœ(˜(Kšœ(˜(Kšœ*˜*Kšœ2˜2Kšœ6˜6Kšœ.˜.Kšœ.˜.Kšœ.˜.Kšœ<˜˜>Kšœ4˜4Kšœ2˜2Kšœ0˜0Kšœ6˜6Kšœ8˜8K˜Kšœ.˜.Kšœ.˜.KšœC˜CKšœC˜CKšœJ˜JKšœD˜DKšœD˜DKšœI˜IKšœI˜IKšœF˜FKšœG˜GKšœK˜KKšœG˜GKšœL˜LKšœK˜KKšœL˜LKšœN˜NKšœN˜NKšœM˜MKšœM˜MKšœM˜MKšœM˜MKšœP˜PK˜KšœUœB˜›K˜K˜—šžœ˜"K˜Kšœ œ˜Kšœ œ˜Kšœœ˜Kšœœ˜Kšœœ˜Kšœœ˜Kšœœ˜Kš œœœœœœ˜IKšœœ˜Kšœœ˜Kšœœ˜Kšœœ˜Kšœ œ˜Kšœ œ˜Kš œœœœœœ˜IKšœ œ˜Kšœ œ˜K˜Kšœ˜Kšœ˜Kšœ˜Kšœ˜Kšœ˜šœœœ ˜Kšœ˜Kšœ˜Kšœ9˜9K˜Kšœ˜—Kšœ˜Kšœ˜Kšœ˜K˜Kšœ˜Kšœ˜Kšœ˜šœœœ ˜šœœœ ˜Kšœ˜Kšœ˜Kšœœ˜Kšœ˜Kšœ˜K˜Kšœ˜—Kšœ˜—Kšœ˜Kšœ˜Kšœœ˜šœœœ ˜šœœœ ˜Kšœ˜Kšœ˜K˜Kšœ˜—Kšœ˜—Kšœ˜K˜Kšœ œ˜Kšœ˜Kšœ˜Kšœ˜Kšœœ˜Kšœ˜Kšœ˜Kšœ˜Kšœ˜šœœœ ˜šœœœ ˜Kšœ˜Kšœ˜Kšœœ˜Kšœœ˜&Kšœ˜K˜Kšœ˜—Kšœ˜—Kšœ˜Kšœ˜Kšœ˜Kšœ˜Kšœ˜K˜Kšœ œ˜Kšœ œ˜Kšœ˜Kšœ˜š œœ œœ ˜#Kšœœ˜Kšœœ˜Kšœ˜K˜K˜Kšœœ˜Kšœœ˜K˜K˜Kšœ œ˜Kšœ˜Kšœ˜K˜K˜Kšœ œ˜K˜Kšœ˜—Kšœœ˜Kšœœ˜Kšœœ˜šœœœ ˜Kšœ œ˜K˜K˜Kšœ œ˜K˜K˜Kšœ œ˜Kšœœ˜"Kšœœ#˜.K˜K˜Kšœ œ˜K˜Kšœ˜—Kšœœ˜Kšœœ˜Kšœœ˜š œœ œœ ˜#Kšœ œ˜K˜K˜Kšœ œ˜K˜K˜Kšœ œ˜Kšœ˜Kšœ ˜ K˜K˜Kšœ œ˜K˜Kšœ˜—Kšœ˜Kšœ˜K˜Kšœ˜Kšœ˜Kšœœ˜Kšœœ˜šœœœ˜Kšœ˜Kšœ˜Kšœ˜Kš œœœœœœ˜2Kš œœœœœœœ˜Kš œœœœœœœ˜?Kš œœœœœœœ˜?K˜Kšœ˜—Kšœœ˜Kšœœ˜šœœœ˜Kšœ˜Kšœ˜Kš œœœœœœ˜1Kš œœœœœœœ˜;Kš œœœœœœ˜1Kš œœœœœœœ˜;Kš œœœœœœœ˜?Kš œœœœœœœ˜?K˜Kšœ˜—Kšœ˜—K˜Kšœ2˜2K˜Kšœ˜—…—²+