DIRECTORY CoreCreate, CoreOps, Logic, LogicUtils, Static, Sisyph; LogicCounterImpl: CEDAR PROGRAM IMPORTS CoreCreate, CoreOps, Logic, LogicUtils, Static, Sisyph EXPORTS Logic = BEGIN OPEN Logic, CoreCreate; CounterName: ROPE = "Counter"; Counter: PUBLIC PROC [b: NAT] RETURNS [ct: CellType] = { counter1B: CellType _ LogicUtils.Extract["counter1B.sch", TRUE]; -- designed by Alfred insts: CellInstances _ NIL; IF b=0 THEN LogicUtils.Error["Please provide the number of bits for the counter"]; IF b=1 THEN LogicUtils.Error["Sorry, but a counter must have more than one bit"]; FOR i: NAT IN [0..b) DO insts _ CONS[ Instance[counter1B, ["dataIn", Index["Input", i]], ["Output", Index["Output", i]], ["carryIn", IF i=b-1 THEN "Cin" ELSE Index["carry", i]], ["carryOut", IF i=0 THEN "Cout" ELSE Index["carry", i-1]], ["nCount", "s1"], ["LoadOrDown", "s0"]], insts]; ENDLOOP; ct _ Cell[ name: CounterName, public: Wires["Vdd", "Gnd", "s0", "s1", "Cin", "Cout", "CK", Seq["Input", b], Seq["Output", b]], onlyInternal: Wires[Seq["carry", b-1]], instances: insts]; }; CounterUpName: ROPE = "CounterUp"; CounterUp: PUBLIC PROC [b: NAT] RETURNS [ct: CellType] = { ctCell: CellType _ LogicUtils.Extract["counterUp1B.sch", TRUE]; ctCtrl: CellType; insts: CellInstances; input, output, nOutput, carry, cout: Wire; IF b=0 THEN LogicUtils.Error["Please provide the number of bits for the up counter"]; IF b=1 THEN LogicUtils.Error["Sorry, but a counter must have more than one bit"]; Sisyph.Store[LogicUtils.cx, "publicD", NEW[NAT_IF b<4 THEN 1 ELSE b/4]]; ctCtrl _ LogicUtils.Extract["counterUp1BCtrl.sch"]; insts _ LIST[Instance[ctCtrl]]; input _ Seq["Input", b]; output _ Seq["Output", b]; nOutput _ Seq["nOutput", b]; carry _ Seq["carry", b]; cout _ CoreOps.SetShortWireName[carry[0], "Cout"]; FOR i: NAT IN [0..b) DO insts _ CONS[ Instance[ctCell, ["Q", output[i]], ["nQ", nOutput[i]], ["input", input[i]], ["carryIn", IF i=b-1 THEN "Cin" ELSE carry[i+1]], ["carryOut", carry[i]], ["load", "load"], ["count", "count"], ["en", "en"], ["nEn", "nEn"], ["CK", "CK"]], insts]; ENDLOOP; ct _ Cell[ name: CounterUpName, public: Wires["Vdd", "Gnd", "CK", "Load", "Count", "Cin", cout, input, output, nOutput], onlyInternal: Wires["load", "count", "en", "nEn", carry ], instances: insts]; }; ShRegName: ROPE = "ShReg"; ShRegLeft: PUBLIC PROC [b: NAT] RETURNS [ct: CellType] = { shCell: CellType _ LogicUtils.Extract["shReg1B.sch", TRUE]; shCtrl: CellType; insts: CellInstances; output, outMSB: Wire; IF b=0 THEN LogicUtils.Error["Please provide the number of bits for the shift register"]; IF b=1 THEN LogicUtils.Error["A shift register must have more than one bit"]; Sisyph.Store[LogicUtils.cx, "publicD", NEW[NAT_IF b<4 THEN 1 ELSE b/4]]; shCtrl _ LogicUtils.Extract["shRegCtrl.sch"]; insts _ LIST[Instance[shCtrl]]; output _ Seq["Output", b]; outMSB _ CoreOps.SetShortWireName[output[0], "outMSB"]; FOR i: NAT IN [0..b) DO insts _ CONS[ Instance[shCell, ["Q", output[i]], ["prev", IF i=b-1 THEN "inLSB" ELSE output[i+1]], ["nQ", Index["nOutput", i]], ["input", Index["Input", i]], ["load", "load"], ["shift", "shift"], ["en", "en"], ["nEn", "nEn"], ["CK", "CK"]], insts]; ENDLOOP; ct _ Cell[ name: ShiftRegName, public: Wires["Vdd", "Gnd", "CK", "Load", "Shift", "inLSB", outMSB, Seq["Input", b], output, Seq["nOutput", b]], onlyInternal: Wires["load", "shift", "en", "nEn"], instances: insts]; }; ShiftRegName: ROPE = "ShiftReg"; ShiftReg: PUBLIC PROC [b: NAT] RETURNS [ct: CellType] = { ff: CellType _ FF4[]; insts: CellInstances _ NIL; fake: Wire _ Static.UnconnectedOK[Seq["fake", b]]; IF b=0 THEN LogicUtils.Error["Please provide the number of bits for the shift register"]; IF b=1 THEN LogicUtils.Error["A shift register must have more than one bit"]; FOR i: NAT IN [0..b) DO insts _ CONS[ Instance[ff, ["D0", IF i=0 THEN "inR" ELSE Index["Output", i-1]], ["D1", IF i=b-1 THEN "inL" ELSE Index["Output", i+1]], ["D2", Index["Output", i]], ["D3", Index["Input", i]], ["Q", Index["Output", i]], ["NQ", Index[fake, i]], ["s0", "s0"], ["s1", "s0"], ["s2", "s1"]], insts]; ENDLOOP; ct _ Cell[ name: ShiftRegName, public: Wires["Vdd", "Gnd", "s0", "s1", "CK", "inL", "inR", Seq["Input", b], Seq["Output", b]], onlyInternal: Wires[fake], instances: insts]; }; END. ´LogicCounterImpl.mesa Copyright c 1986 by Xerox Corporation. All rights reserved. Last Edited by: Louis Monier January 8, 1987 1:45:05 pm PST Barth, October 22, 1986 11:48:51 am PDT Counter CounterUp TestCounterUp: PROC [b: NAT] RETURNS [ct: CellType] = { ctCell: CellType _ LogicUtils.SCBlock[LogicUtils.Extract["counterUp1B.sch", TRUE]]; ctCtrl: CellType; insts: CellInstances; input, output, nOutput, carry, cout: Wire; IF b=0 THEN LogicUtils.Error["Please provide the number of bits for the up counter"]; IF b=1 THEN LogicUtils.Error["Sorry, but a counter must have more than one bit"]; Sisyph.Store[LogicUtils.cx, "publicD", NEW[NAT_IF b<4 THEN 1 ELSE b/4]]; ctCtrl _ LogicUtils.Extract["counterUp1BCtrl.sch"]; insts _ LIST[Instance[ctCtrl]]; input _ Seq["Input", b]; output _ Seq["Output", b]; nOutput _ Seq["nOutput", b]; carry _ Seq["carry", b]; cout _ CoreOps.SetShortWireName[carry[0], "Cout"]; FOR i: NAT IN [0..b) DO insts _ CONS[ Instance[ctCell, ["Q", output[i]], ["nQ", nOutput[i]], ["input", input[i]], ["carryIn", IF i=b-1 THEN "Cin" ELSE carry[i+1]], ["carryOut", carry[i]], ["load", "load"], ["count", "count"], ["freeze", "freeze"], ["CK", "CK"]], insts]; ENDLOOP; ct _ Cell[ name: CounterUpName, public: Wires["Vdd", "Gnd", "CK", "Load", "Count", "Cin", cout, input, output, nOutput], onlyInternal: Wires["load", "count", "freeze", carry ], instances: insts]; }; Left-ShiftReg ShiftReg [] _ Counter[2]; [] _ ShiftReg[2]; Êœ– "cedar" style˜codešœ™Kšœ Ïmœ1™Kšžœ˜ Kšœžœžœ˜—headšŸ™KšŸœžœ ˜K˜š Ÿœžœžœžœžœ˜8Kšœ:žœÏc˜VKšœžœ˜KšžœžœG˜RKšžœžœF˜Qšžœžœžœž˜šœžœ˜ šœ˜Kšœ?˜?Kšœžœžœžœ˜9Kšœ žœžœžœ˜;Kšœ)˜)—Kšœ˜—Kšžœ˜—šœ ˜ Kšœ˜Kšœa˜aKšœ(˜(Kšœ˜—Kšœ˜——šŸ ™ KšŸ œžœ˜"K˜š Ÿ œžœžœžœžœ˜:Kšœ9žœ˜?Kšœ˜Kšœ˜Kšœ*˜*KšžœžœJ˜UKšžœžœF˜QKšœ'žœžœžœžœžœ˜HKšœ3˜3Kšœžœ˜Kšœ˜Kšœ˜Kšœ˜Kšœ˜Kšœ2˜2šžœžœžœž˜šœžœ˜ šœ˜Kšœ˜Kšœ˜Kšœ˜Kšœžœžœžœ˜2Kšœ˜KšœS˜S—Kšœ˜—Kšžœ˜—šœ ˜ Kšœ˜KšœY˜YKšœ:˜:Kšœ˜—Kšœ˜—šŸ œžœžœžœ™7KšœLžœ™SKšœ™Kšœ™Kšœ*™*KšžœžœJ™UKšžœžœF™QKšœ'žœžœžœžœžœ™HKšœ3™3Kšœžœ™Kšœ™Kšœ™Kšœ™Kšœ™Kšœ2™2šžœžœžœž™šœžœ™ šœ™Kšœ™Kšœ™Kšœ™Kšœžœžœžœ™2Kšœ™KšœK™K—Kšœ™—Kšžœ™—šœ ™ Kšœ™KšœY™YKšœ7™7Kšœ™—Kšœ™——šŸ ™ KšŸ œžœ˜K˜š Ÿ œžœžœžœžœ˜:Kšœ5žœ˜;Kšœ˜Kšœ˜Kšœ˜KšžœžœN˜YKšžœžœB˜MKšœ'žœžœžœžœžœ˜HKšœ-˜-Kšœžœ˜Kšœ˜Kšœ7˜7šžœžœžœž˜šœžœ˜ šœ˜Kšœ˜Kšœ žœžœ žœ˜2Kšœ˜Kšœ˜KšœS˜S—Kšœ˜—Kšžœ˜—šœ ˜ Kšœ˜Kšœq˜qKšœ2˜2Kšœ˜—Kšœ˜——šŸ™KšŸœžœ˜ K˜š Ÿœžœžœžœžœ˜9Kšœ˜Kšœžœ˜Kšœ2˜2KšžœžœN˜YKšžœžœB˜Mšžœžœžœž˜šœžœ˜ šœ ˜ Kšœžœžœžœ˜5Kšœžœžœžœ˜7Kšœ˜Kšœ˜Kšœ˜Kšœ˜Kšœ+˜+—Kšœ˜—Kšžœ˜—šœ ˜ Kšœ˜Kšœ`˜`Kšœ˜Kšœ˜—Kšœ˜——K˜Kšžœ˜K™Kšœ™Kšœ™K˜—…—À