StdCellsCmosB.mesa
Copyright © 1986 by Xerox Corporation. All rights reserved.
Louis Monier, July 14, 1986 1:25:29 pm PDT
Last Edited by: Louis Monier January 7, 1987 5:47:43 pm PST
-- Defines every cell of a standard cell library for CMosB (2m CMOS with two levels of metal, fabricated by both VTI and ICL). Will be used by the library "Logic". Layout of first cells courtesy of Christian Jacobi. As much as possible, the cells follow the terminology used in the "CMOS Standard Cell User's Guide and Data Manual" from ED (January1986, Release 2.0).
DIRECTORY
CD, CDImports, Core, CoreDirectory, PW, PWCore, Rope, Sisyph;
StdCellsCmosB: CEDAR PROGRAM
IMPORTS CDImports, CoreDirectory, PW, PWCore, Sisyph
~ BEGIN
CellType: TYPE = Core.CellType;
ROPE: TYPE = Rope.ROPE;
Library
-- The source of schematics and layout
schDesignName: ROPE = "SCLibCMOSB";
schDesign: CD.Design;
schDesignCx: Sisyph.Context;
-- The library, in the sense of CoreDirectory, i.e. a collection of cellTypes
libName: ROPE = "CMOSB"; -- known to the designer
lib: CoreDirectory.Library;
Extract: PROC [name: ROPE] RETURNS [cellType: CellType] ~ {
cellType ← Sisyph.ExtractSchematicByName[name: name, cx: schDesignCx];
};
MakeSCCell: PROC [name, schName: ROPE] ~ {
ct: CellType ← Extract[schName]; -- extract schematics from schDesign
PWCore.SetGet[ct, schDesign]; -- specify the layout
[] ← CoreDirectory.Insert[lib, name, ct]; -- register the cell in the library
};
Initialization
schDesign ← PW.OpenDesign[schDesignName];
[] ← CDImports.Load[into: schDesign, importeeName: "SSI"];
schDesignCx ← Sisyph.Create[schDesign];
lib ← CoreDirectory.RegisterLibrary[CoreDirectory.CreateLibrary[], libName];
Needed by the router
MakeSCCell["feedthru", "Feedthru.sch"];
Basic combinatorial cells
MakeSCCell["gnd", "C2GD00A.sch"];
MakeSCCell["vdd", "C2VD00A.sch"];
MakeSCCell["inv", "C2IV00A.sch"];
MakeSCCell["invBuffer", "C2IV00B.sch"];
MakeSCCell["tstDriver", "C2BD02A.sch"];
MakeSCCell["and2", "C2AN02A.sch"];
MakeSCCell["and3", "C2AN03A.sch"];
MakeSCCell["and4", "C2AN04A.sch"];
MakeSCCell["nand2", "C2NA02A.sch"];
MakeSCCell["nand3", "C2NA03A.sch"];
MakeSCCell["nand4", "C2NA04A.sch"];
MakeSCCell["or2", "C2OR02A.sch"];
MakeSCCell["or3", "C2OR03A.sch"];
MakeSCCell["or4", "C2OR04A.sch"];
MakeSCCell["nor2", "C2NO02A.sch"];
MakeSCCell["nor3", "C2NO03A.sch"];
MakeSCCell["nor4", "C2NO04A.sch"];
MakeSCCell["xor2", "C2XR02A.sch"];
MakeSCCell["xnor2", "C2XN02A.sch"];
MakeSCCell["a22o2i", "a22o2i.sch"];
MakeSCCell["o22a2i", "o22a2i.sch"];
MakeSCCell["a21o2i", "a21o2i.sch"];
Flip-flops and Latches
MakeSCCell["ff", "ff.sch"];
MakeSCCell["ffEn", "ffEn.sch"];
MakeSCCell["dLatch", "dLatch.sch"];
END.