
<<SSIRoseTest.mesa>>
    <<Copyright © 1986 by Xerox Corporation.  All rights reserved.>>
    <<Barth, June 13, 1986 3:12:10 pm PDT>>
    <<Last Edited by: Louis Monier August 7, 1986 7:45:51 pm PDT>>
    <<>>
    DIRECTORY Core,
    CoreCreate, SSI,
    CoreOps, Ports, Rosemary, RosemaryUser
    <<, PW, Sisyph>>
    ;

    SSIRoseTest: CEDAR PROGRAM
        IMPORTS
        CoreCreate, SSI,
        CoreOps, Ports, Rosemary, RosemaryUser
        <<, PW, Sisyph>>
        = BEGIN

    fileName: Core.ROPE _ "///Users/Barth.pa/DA/SSI";
    Vdd: NAT;
    Gnd: NAT;
    Input0: NAT;
    Input1: NAT;
    Output: NAT;

    XOr2Test: RosemaryUser.TestProc = {
    Step: TYPE = [0..4);
    levIn0: ARRAY Step OF Ports.Level    _ [L, L, H, H];  
    levIn1: ARRAY Step OF Ports.Level    _ [L, H, L, H];
    levOut: ARRAY Step OF Ports.Level    _ [L, H, H, L];

    p[Input0].l _ p[Input1].l _ L;

    Eval[! Rosemary.Stop => RESUME];
    FOR step: Step IN Step DO
    p[Input0].l _ levIn0[step];
    p[Input1].l _ levIn1[step];
    p[Output].l _ levOut[step];
    Eval[];
    ENDLOOP;
        };

    Test: PROC RETURNS [ct: Core.CellType] = {
        ct _ CoreCreate.Cell[
            name: "XOr",
            public: CoreCreate.Wires["Vdd", "Gnd", "Input0", "Input1", "Output"],
            onlyInternal: CoreCreate.Wires["nor", "pstack", "nstack"],
            instances: LIST [
                CoreCreate.Instance[SSI.NOr[],
                    ["Input[0]", "Input0"], ["Input[1]", "Input1"], ["nOutput", "nor"]],
                CoreCreate.Instance[CoreCreate.Transistor[pE],
                    ["gate", "Input0"], ["ch1", "Vdd"], ["ch2", "pstack"]],
                CoreCreate.Instance[CoreCreate.Transistor[pE],
                    ["gate", "Input1"], ["ch1", "Vdd"], ["ch2", "pstack"]],
                CoreCreate.Instance[CoreCreate.Transistor[pE],
                    ["gate", "nor"], ["ch1", "pstack"], ["ch2", "Output"]],
                CoreCreate.Instance[CoreCreate.Transistor[nE],
                    ["gate", "Input1"], ["ch1", "Output"], ["ch2", "nstack"]],
                CoreCreate.Instance[CoreCreate.Transistor[nE],
                    ["gate", "Input0"], ["ch1", "nstack"], ["ch2", "Gnd"]],
                CoreCreate.Instance[CoreCreate.Transistor[nE],
                    ["gate", "nor"], ["ch1", "Output"], ["ch2", "Gnd"]]]];
        <<ct _ Sisyph.ExtractSchematicByName["XOr2.sch", Sisyph.Create[PW.OpenDesign[fileName], Sisyph.defaultGlobalNames]];>>
        Vdd _ CoreOps.GetWireIndex[ct.public, "Vdd"];
        Gnd _ CoreOps.GetWireIndex[ct.public, "Gnd"];
        Input0 _ CoreOps.GetWireIndex[ct.public, "Input0"];
        Input1 _ CoreOps.GetWireIndex[ct.public, "Input1"];
        Output _ CoreOps.GetWireIndex[ct.public, "Output"];
        [] _ Rosemary.SetFixedWire[ct.public[Vdd], H];
        [] _ Rosemary.SetFixedWire[ct.public[Gnd], L];
        FOR i: NAT IN [0..ct.public.size) DO
            [] _ Ports.InitPort[wire: ct.public[i], levelType: l];
        ENDLOOP;
        [] _ Ports.InitTesterDrive[wire: ct.public[Input0], initDrive: force];
        [] _ Ports.InitTesterDrive[wire: ct.public[Input1], initDrive: force];
        [] _ Ports.InitTesterDrive[wire: ct.public[Output], initDrive: expect];
        [] _ RosemaryUser.TestProcedureViewer[name: "XOr Tester", cellType: ct, testButtons: LIST["XOr2Test"], displayWires: 
        RosemaryUser.DisplayCellTypePortLeafWires[cellType: ct], flatten: TRUE];
        };

    RosemaryUser.RegisterTestProc["XOr2Test", XOr2Test];

    END.
<<>>