[Cyan]<DATools6.1>CellLibraries>MSITest.mesa!2

MSITest.mesa

Barth, June 13, 1986 3:13:17 pm PDT

Last Edited by: Louis Monier August 7, 1986 8:14:01 pm PDT

DIRECTORY BitOps, Core, Ports, Rosemary, RosemaryUser;

MSITest: CEDAR PROGRAM

IMPORTS BitOps, Ports, Rosemary, RosemaryUser =

BEGIN

Vdd: NAT;

Gnd: NAT;

PhA: NAT;

PhB: NAT;

AEqB: NAT;

TriDrive: NAT;

TriDriveIn: NAT;

TriOut: NAT;

RegOut: NAT;

Select: NAT;

ClockedSelect: NAT;

BusMuxOut: NAT;

MuxOut: NAT;

AddA: NAT;

AddB: NAT;

COut: NAT;

LoadShift: NAT;

LeftShift: NAT;

LeftIn: NAT;

RightIn: NAT;

ShiftOut: NAT;

CounterLoad: NAT;

CountUp: NAT;

CounterOutput: NAT;

RegisterLoad: NAT;

RegisterAdr: NAT;

RegisterOutput: NAT;

MultiLoad: NAT;

WriteAdr: NAT;

ReadAdr: NAT;

MultiInput: NAT;

MultiOutput: NAT;

Init: PROC [ct: Core.CellType] = {

sim: Rosemary.Simulation;

Vdd ← Ports.PortIndex[ct.public, "Vdd"];

Gnd ← Ports.PortIndex[ct.public, "Gnd"];

PhA ← Ports.PortIndex[ct.public, "PhA"];

PhB ← Ports.PortIndex[ct.public, "PhB"];

AEqB ← Ports.PortIndex[ct.public, "AEqB"];

TriDrive ← Ports.PortIndex[ct.public, "TriDrive"];

TriDriveIn ← Ports.PortIndex[ct.public, "TriDriveIn"];

TriOut ← Ports.PortIndex[ct.public, "TriOut"];

RegOut ← Ports.PortIndex[ct.public, "RegOut"];

Select ← Ports.PortIndex[ct.public, "Select"];

ClockedSelect ← Ports.PortIndex[ct.public, "ClockedSelect"];

BusMuxOut ← Ports.PortIndex[ct.public, "BusMuxOut"];

MuxOut ← Ports.PortIndex[ct.public, "MuxOut"];

AddA ← Ports.PortIndex[ct.public, "AddA"];

AddB ← Ports.PortIndex[ct.public, "AddB"];

COut ← Ports.PortIndex[ct.public, "COut"];

LoadShift ← Ports.PortIndex[ct.public, "LoadShift"];

LeftShift ← Ports.PortIndex[ct.public, "LeftShift"];

LeftIn ← Ports.PortIndex[ct.public, "LeftIn"];

RightIn ← Ports.PortIndex[ct.public, "RightIn"];

ShiftOut ← Ports.PortIndex[ct.public, "ShiftOut"];

CounterLoad ← Ports.PortIndex[ct.public, "CounterLoad"];

CountUp ← Ports.PortIndex[ct.public, "CountUp"];

CounterOutput ← Ports.PortIndex[ct.public, "CounterOutput"];

RegisterLoad ← Ports.PortIndex[ct.public, "RegisterLoad"];

RegisterAdr ← Ports.PortIndex[ct.public, "RegisterAdr"];

RegisterOutput ← Ports.PortIndex[ct.public, "RegisterOutput"];

MultiLoad ← Ports.PortIndex[ct.public, "MultiLoad"];

WriteAdr ← Ports.PortIndex[ct.public, "WriteAdr"];

ReadAdr ← Ports.PortIndex[ct.public, "ReadAdr"];

MultiInput ← Ports.PortIndex[ct.public, "MultiInput"];

MultiOutput ← Ports.PortIndex[ct.public, "MultiOutput"];

[] ← Rosemary.SetFixedWire[ct.public[Vdd], H];

[] ← Rosemary.SetFixedWire[ct.public[Gnd], L];

[] ← Ports.InitTesterDrive[wire: ct.public[PhA], initDrive: force];

[] ← Ports.InitTesterDrive[wire: ct.public[PhB], initDrive: force];

[] ← Ports.InitTesterDrive[wire: ct.public[TriDriveIn], initDrive: force];

[] ← Ports.InitTesterDrive[wire: ct.public[AddA], initDrive: force];

[] ← Ports.InitTesterDrive[wire: ct.public[AddB], initDrive: force];

[] ← Ports.InitTesterDrive[wire: ct.public[LoadShift], initDrive: force];

[] ← Ports.InitTesterDrive[wire: ct.public[LeftShift], initDrive: force];

[] ← Ports.InitTesterDrive[wire: ct.public[LeftIn], initDrive: force];

[] ← Ports.InitTesterDrive[wire: ct.public[RightIn], initDrive: force];

[] ← Ports.InitTesterDrive[wire: ct.public[CounterLoad], initDrive: force];

[] ← Ports.InitTesterDrive[wire: ct.public[CountUp], initDrive: force];

[] ← Ports.InitTesterDrive[wire: ct.public[RegisterLoad], initDrive: force];

[] ← Ports.InitTesterDrive[wire: ct.public[RegisterAdr], initDrive: force];

[] ← Ports.InitTesterDrive[wire: ct.public[MultiLoad][0], initDrive: force];

[] ← Ports.InitTesterDrive[wire: ct.public[WriteAdr][0][0], initDrive: force];

[] ← Ports.InitTesterDrive[wire: ct.public[WriteAdr][0][1], initDrive: force];

[] ← Ports.InitTesterDrive[wire: ct.public[ReadAdr][0][0], initDrive: force];

[] ← Ports.InitTesterDrive[wire: ct.public[ReadAdr][0][1], initDrive: force];

[] ← Ports.InitTesterDrive[wire: ct.public[ReadAdr][1][0], initDrive: force];

[] ← Ports.InitTesterDrive[wire: ct.public[ReadAdr][1][1], initDrive: force];

[] ← Ports.InitTesterDrive[wire: ct.public[MultiInput][0][0], initDrive: force];

sim ← RosemaryUser.TestProcedureViewer[name: "MSI Tester", cellType: ct, testButtons: LIST["TestMSI"], displayWires: RosemaryUser.DisplayCellTypePortLeafWires[ct], flatten: TRUE];

};

TestMSI: RosemaryUser.TestProc = {

p[PhA].b ← FALSE;

p[PhB].b ← FALSE;

p[TriDriveIn].b ← TRUE;

p[LoadShift].b ← TRUE;

p[CounterLoad].b ← TRUE;

p[RegisterLoad].b ← TRUE;

p[MultiLoad][0].b ← TRUE;

Eval[! Rosemary.Stop => IF data = $BoolWireHasX THEN RESUME ELSE REJECT];

p[LoadShift].b ← FALSE;

p[CounterLoad].b ← FALSE;

p[RegisterLoad].b ← FALSE;

p[MultiLoad][0].b ← FALSE;

p[PhA].b ← FALSE;

p[PhB].b ← TRUE;

Eval[! Rosemary.Stop => IF data = $BoolWireHasX THEN RESUME ELSE REJECT];

p[PhA].b ← TRUE;

p[PhB].b ← FALSE;

p[BusMuxOut].d ← expect;

p[BusMuxOut].c ← 5;

p[RegOut].d ← expect;

p[ClockedSelect].d ← expect;

p[Select].d ← expect;

FOR b: NAT IN [0..16) DO

p[AddB].c ← b;

p[RegOut].c ← b;

p[Select].c ← p[ClockedSelect].c ← BitOps.TwoToThe[15-b];

Eval[];

ENDLOOP;

p[RegOut].d ← none;

p[ClockedSelect].d ← none;

p[Select].d ← none;

p[TriOut].d ← expect;

p[COut].d ← expect;

p[AEqB].d ← expect;

FOR a: NAT IN [0..16) DO

FOR b: NAT IN [0..16) DO

p[AddA].c ← a;

p[AddB].c ← b;

p[TriOut].c ← (a+b) MOD 16;

p[COut].b ← (a+b) >= 16;

p[AEqB].b ← a=b;

Eval[];

ENDLOOP;

p[COut].d ← none;

p[AEqB].d ← none;

p[TriDriveIn].b ← FALSE;

FOR a: NAT IN [0..16) DO

FOR b: NAT IN [0..16) DO

p[AddA].c ← a;

p[AddB].c ← b;

Eval[];

ENDLOOP;

p[TriOut].d ← none;

p[PhA].b ← FALSE;

p[BusMuxOut].d ← expect;

p[MuxOut].d ← expect;

p[TriDrive].d ← expect;

p[TriDrive].b ← FALSE;

p[RegOut].d ← expect;

p[RegOut].c ← 15;

p[ClockedSelect].d ← expect;

p[ClockedSelect].c ← 0;

FOR a: NAT IN [0..16) DO

FOR b: NAT IN [0..16) DO

p[AddA].c ← a;

p[AddB].c ← b;

p[BusMuxOut].c ← (a+b) MOD 16;

p[TriDriveIn].b ← NOT p[TriDriveIn].b;

p[MuxOut].b ← (a+b) >= 16;

Eval[];

ENDLOOP;

p[BusMuxOut].d ← none;

p[MuxOut].d ← none;

p[TriDrive].d ← none;

p[RegOut].d ← none;

p[ClockedSelect].d ← none;

p[PhA].b ← FALSE;

p[PhB].b ← FALSE;

p[CounterOutput].d ← expect;

p[ShiftOut].d ← expect;

FOR b: NAT DECREASING IN [0..16) DO

p[CounterLoad].b ← TRUE;

p[LoadShift].b ← TRUE;

p[AddB].c ← b;

Eval[];

p[CounterLoad].b ← FALSE;

p[LoadShift].b ← FALSE;

Eval[];

p[PhB].b ← TRUE;

p[CounterOutput].c ← b;

p[ShiftOut].c ← b;

Eval[];

p[PhB].b ← FALSE;

Eval[];

ENDLOOP;

p[CountUp].b ← TRUE;

p[LeftShift].b ← TRUE;

p[RightIn].b ← TRUE;

FOR b: NAT IN [0..16) DO

p[PhA].b ← TRUE;

Eval[];

p[PhA].b ← FALSE;

Eval[];

p[PhB].b ← TRUE;

p[CounterOutput].c ← (b+1) MOD 16;

IF b<4 THEN p[ShiftOut].c ← 2*p[ShiftOut].c+1;

Eval[];

p[PhB].b ← FALSE;

Eval[];

ENDLOOP;

p[CountUp].b ← FALSE;

p[LeftShift].b ← FALSE;

p[LeftIn].b ← FALSE;

FOR b: NAT DECREASING IN [0..16) DO

p[PhA].b ← TRUE;

Eval[];

p[PhA].b ← FALSE;

Eval[];

p[PhB].b ← TRUE;

p[CounterOutput].c ← b;

p[ShiftOut].c ← p[ShiftOut].c/2;

Eval[];

p[PhB].b ← FALSE;

Eval[];

ENDLOOP;

p[CounterOutput].d ← none;

p[ShiftOut].d ← none;

p[RegisterOutput].d ← expect;

p[MultiOutput].d ← expect;

p[RegisterLoad].b ← TRUE;

p[MultiLoad][0].b ← TRUE;

FOR b: NAT IN [0..4) DO

p[RegisterAdr].c ← b;

p[AddB].c ← b;

p[RegisterOutput].c ← b;

p[WriteAdr][0][0].b ← IF b>1 THEN TRUE ELSE FALSE;

p[WriteAdr][0][1].b ← IF (b MOD 2) = 1 THEN TRUE ELSE FALSE;

p[ReadAdr][0][0].b ← IF b>1 THEN TRUE ELSE FALSE;

p[ReadAdr][0][1].b ← IF (b MOD 2) = 1 THEN TRUE ELSE FALSE;

p[ReadAdr][1][0].b ← IF b>1 THEN TRUE ELSE FALSE;

p[ReadAdr][1][1].b ← IF (b MOD 2) = 1 THEN TRUE ELSE FALSE;

p[MultiInput][0][0].b ← IF (b MOD 2) = 1 THEN TRUE ELSE FALSE;

p[MultiOutput][0][0].b ← IF (b MOD 2) = 1 THEN TRUE ELSE FALSE;

p[MultiOutput][1][0].b ← IF (b MOD 2) = 1 THEN TRUE ELSE FALSE;

Eval[];

ENDLOOP;

p[RegisterLoad].b ← FALSE;

p[MultiLoad][0].b ← FALSE;

FOR b: NAT IN [0..4) DO

p[RegisterAdr].c ← b;

p[RegisterOutput].c ← b;

p[ReadAdr][0][0].b ← IF b>1 THEN TRUE ELSE FALSE;

p[ReadAdr][0][1].b ← IF (b MOD 2) = 1 THEN TRUE ELSE FALSE;

p[ReadAdr][1][0].b ← IF b>1 THEN TRUE ELSE FALSE;

p[ReadAdr][1][1].b ← IF (b MOD 2) = 1 THEN TRUE ELSE FALSE;

p[MultiOutput][0][0].b ← IF (b MOD 2) = 1 THEN TRUE ELSE FALSE;

p[MultiOutput][1][0].b ← IF (b MOD 2) = 1 THEN TRUE ELSE FALSE;

Eval[];

ENDLOOP;

};

RosemaryUser.RegisterTestProc["TestMSI", TestMSI];

END.