<> <> <> <<>> DIRECTORY CoreCreate; MSI: CEDAR DEFINITIONS = BEGIN OPEN CoreCreate; <<>> Latch: PROC RETURNS [ct: CellType]; <<"Vdd", "Gnd", "Load", "Input", "Output">> Register: PROC [b: NAT] RETURNS [ct: CellType]; <<"Vdd", "Gnd", "Load", Seq["Input", b], Seq["Output", b]>> Constant: PROC [b: NAT, v: INT] RETURNS [ct: CellType]; <<"Vdd", "Gnd", Seq["Output", b]>> <

> Multiplexor: PROC [i: NAT _ 2] RETURNS [ct: CellType]; <> <<>> BusMultiplexor: PROC [b: NAT, i: NAT _ 2] RETURNS [ct: CellType]; <> <<>> Buffers: PROC [b: NAT] RETURNS [ct: CellType]; <<"Vdd", "Gnd", Seq["Input", b], Seq["Output", b]>> TristateBuffers: PROC [b: NAT] RETURNS [ct: CellType]; <<"Vdd", "Gnd", "Drive", Seq["Input", b], Seq["Output", b]>> Adder: PROC [b: NAT] RETURNS [ct: CellType]; <<"Vdd", "Gnd", "CarryIn", Seq["A", b], Seq["B", b], Seq["Sum", b], "CarryOut">> Comparator: PROC [b: NAT] RETURNS [ct: CellType]; <<"Vdd", "Gnd", Seq["A", i], Seq["B", i], "AEqB">> Decoder: PROC [a: NAT, s: NAT _ 0] RETURNS [ct: CellType]; <<"Vdd", "Gnd", Seq["Address", a], Seq["Select", s]>> < s _ 2**a>> <<>> ClockedDecoder: PROC [a: NAT, s: NAT _ 0] RETURNS [ct: CellType]; <<"Vdd", "Gnd", Seq["Address", a], Seq["Select", s], "Clock">> < s _ 2**a>> < 2**a => ERROR>> <<>> ShiftRegister: PROC [b: NAT] RETURNS [ct: CellType]; <<"Vdd", "Gnd", "ShiftA", "ShiftB", "Load", "LeftNRight", "LeftInput", "RightInput", Seq["Input", b], Seq["Output", b]>> <<>> Counter: PROC [b: NAT] RETURNS [ct: CellType]; <<"Vdd", "Gnd", "CountA", "CountB", "Load", "UpNDown", Seq["Input", b], Seq["Output", b]>> <<>> RegisterFile: PROC [b: NAT, a: NAT, w: NAT _ 0] RETURNS [ct: CellType]; <<"Vdd", "Gnd", "Load", Seq["Address", a], Seq["Input", b], Seq["Output", b]>> <> < w _ 2**a>> < 2**a => ERROR>> <<>> MultiPortRegisterFile: PROC [b: NAT, a: NAT, w: NAT _ 0, rp: NAT _ 1, wp: NAT _ 1] RETURNS [ct: CellType]; <<"Vdd", "Gnd", Seq["Load", wp], Seq["WriteAddress", wp, Seq[size: a]], Seq["ReadAddress", rp, Seq[size: a]], Seq["Input", wp, Seq[size: b]], Seq["Output", rp, Seq[size: b]]>> <> < w _ 2**a>> < 2**a => ERROR>> <<>> END.