1. Introduction
Generalities
The "Logic" library is intended to be used for drawing schematics at a logic level. Each icon comes with a simulation procedure, and either a standard cell decomposition or a standard generator.
All schematics must be drawn in the CMosB technology of ChipNDale, using the comment layer for wires. The menus SPACE-O and SPACE-P contain most of the commands you need. The font Helvetica8 (4/8) is a good one for text.
(*) means I am working on it.
What is public
The icons in the "released" box are public. The name, size, shape of the icon, the position of the pins, and the general semantic are supposed to be stable, i.e. any change will be done with profuse apologies and a lot of advance notice.
What is not public
Anything else in the library, the implementation of Logic, the name of the public wires of an icon, the layout of the standard cells, the notion of time in Rosemary, are all subject to change, and in fact do change all the time to track updates in the DA system, user feedback, performance tuning, ... Do not rely on anything at this level.
What you need to know before starting
You should be familiar with ChipnDale, Sisyph, and Rosemary. Understand icons, structured wires, satellites, ... If the documentation is not sufficient, complain to the author/maintainer.
For composite wires, you should know about the generators put out by Bertrand Serlet (see above). P-middle is the commands to access Composer, Extractor, Range Extractor, and Bus Constructor. As usual, 0 is the high-order bit (wire) and is indicated by an extra-wide pin in the composer. Never, never, never, attempt to edit such icons.
Starting up
Bringover everything (% BringDAUser) and start everything (% Schematics.load). Read in your design (% CDRead MyChip.dale) and, unless you know the library by heart, read also the library (% CDRead Logic.dale). Before you start doing any real work, you can play with the design "TestLogic.dale" as a model.
Now import the icons that you need from "Logic" into your design (cf. ChipNDale documentation to do imports): the (ZX-left-click on icon in library, ZX-middle-click in your design) command to import a cell is the best because you don't have to know the name of the icon, just to point at it. Start drawing!
The library
Information about timing and size will be provided for every cell and macro (*). All cells have a fixed height of 104m. The width is a multiple of 10m called here a track. Input loads are counted in standard loads (= 0.2pF) and output drives in standard drives (= drive of an inverter, i.e. a 2/20 n-device and a 2/50 p-device). All these numbers are subject to changes.
Simulation
For large simulations involving a simulation proc and a test proc, refer to the Rosemary documentation (available only in Basque and Southern Mongolian through Rick Barth, Unlimited Doc. Inc., rm 2218).
For interactive simulation, build a cell including the cell(s) to be tested with testing paraphernalia (roseClock.icon among them). Vdd and Gnd get their value automatically. Beware that the three logic level L, X, and H are used, and that all states are initialized to X.
Which wires do you want to display? Here are the possibilities:
- Every top-level named wires (i.e. part of the internal wire of the top cell) will be displayed. A wire is named if you name it explicitely or if the inherited names do not conflict.
- Using the add command in the Rosemary typescript, you can add to the timing display (oscilloscope) any wire which you can access by name. Familiarity with the commands available in the Rosemary typescript and long-name syntax will help a lot.
Now you can simulate at two different levels. Most macros come with a behavioral procedure which tries hard to reproduce reality, and a decomposition in more primitive cells. The behavioral model of basic cells has been checked and can be reasonably be trusted. The default uses only the basic cells: it is thus slow but quite precise. If you are worried about speed, you can add in the simulation cell an object satellite [Simulation: $Fast] to use top-level behavioral procedures: faster, but not as safe.
Then call "Sisyph Extract and Rosemary" in the SPACE-O menu; your cell will be extracted, Rosemary will create a simulation and a display panel with a typescript and a oscilloscope-like display. If instead you get an error window with no message on the terminal, come and complain for this should not happen.
Start the simulation by bugging "Single Eval" and watch the values on the ports change; for faster action, use "Proceed" and "Interrupt".
Clock generator
By use of sufficiently advanced technology (i.e. magic) the following notion of time is provided: everytime you bug the "single eval" button in the Rosemary panel, the time is incremented by 1.
The clock generator roseClock has access to this "time". It accepts four parameters: up, dn, firstEdge (all integers expressed in time units), and initLow, a boolean specifying the initial state of the clock. The defaults (up ← dn ← firstEdge ← 1; initLow← TRUE) provide a simple tick-tack generator: starting in a low state, it alternates between H and L everytime you bug the "single eval" button.
How to reach infinity: if you need to specify a single pulse and would like to say dn ← infinity, you can use the value LAST[INT] (=2147483647 cycles, which looks like a very long simulation), or by convention -1 will have the same effect.
Oracle: test proc without code
An oracle is a piece of magic which provides stimuli to your circuit and compares the answers. It is exactly a test procedure, and is perfect for testing simple blocks without coding. I said "simple"! If you have more than one page of vectors or need extra features, you need to write a test procedure.
The oracle has three parameters: a name (id), and the format of input and output wires. These wires are structured wires, and you must specify the structure of subwires as follows: if In is made of an atomic wire, a byte, and a 32-bit bus, you specify in ← "0 8 32". Atomic wires (0) are not the same as single-element composite wires (1). If a wire has more structe, you use ( ): in ← "0 8 (0 32)" means that the third wire is made of an atomic wire and a 32-wide bus. There is no restriction on the depth of wires.
Stimuli and expected results are stored on a file, one line per "clock cycle", and ouptuts (stimuli) are on the left, separated from the inputs (expected results) from a vertical bar "|". The name of this file is by default the "id" parameter. To change it, you can type
← Logic.SetOracleFileName["TheIdName", "NewFileName"]
and if you are confused as far as which file is currently used, type
← Logic.GetOracleFileName["TheIdName"]
On every rising edge of the clock, the oracle issues a new set of values. These values are read from your file and reside on the left of the vertical bar. Values are hex numbers extended with X (which means no drive). Valid numbers are 0, 1, 35, 4FFA, X022XX, 3(001X)5F, (0011)(010X): no space inside a value! Values are right-justified, and either truncated or zero-filled. To specify the values for a deeply structured wire, use parentheses and spaces. An example of value for the wire specified above could be 1 3(011X) ( 0 3FF(01X0)0001 ). Don't forget the spaces or the parser will get confused.
On the falling edge of the clock, the input is sampled and compared with the values on the righ-side of the vertical bar. Same format, except that this time X means don't care.
The file is read every time you click the Start button in Rosemary, so you can modify it without re-extracting.
Assertion verification
The icon roseStop has the property that if its input (anywhere on its periphery) is high, then it raises a Rosemary signal. When the Event Window opens, it is possible to update the display by bugging the Update button. One can also proceed by bugging Proceed in the Event Window (not in the Rosemary panel).
Due to the algorithm used by Rosemary, non-race-free circuits can generate glitches which could raise the signal though the final value after the simulation settles would not. To avoid this, the input is sampled on the next Time transition.
Cosmetics
A family of arrows is provided. These arrows are strictly cosmetic and ignored by the extractor.
A contact cell is also provided: it is useful to indicate connections among crossing wires without having to break these wires.
Power supply
For historical reasons, there are two sets of Vdd and Gnd icons: they are now equivalent. The cells providing logic 0 and 1 are automatically inserted by the SC layout system, so don't worry about how many such symbols you use.
The Static checker
It is a good idea to run Static, the static checker, on your design. In order to avoid false errors, mark every unconnected output (for example the complementary output of a register that you do not use) with the unconnected icon, a little black square.
Layout
Finally, layout time! For every standard cell block you must have a cell including the object satellite "Layout: $SC". Public wires: if in this schematics a wire intersects a side of the cell, then the wire corresponding wire(s) in the layout will come out of the same side.
Current restrictions: a wire can be present only on one side; and if a composite wire appears in the internal of the cell, all of its atomic wires must be used (i.e. connected).
Finally poke "Extract and Layout" in the SPACE-O menu, stand back and wait.
2. Simple logic gates
Each one of these gates corresponds to a single standard cell. The "zero-th input" is specified by a thicker wire. When a gate has series transistors (e.g. nand), the zero-th input is the closest from the power supply, e.g. it is the slowest. For a description of the public wire and the parameters, refer to the interface Logic.mesa. Most gates come in two different looks (bubbles before or after).
Inverter, buffer and tristate driver
The inverter, with two different looks, and a tristate driver with complemented enable lines.
Simple Combinatorial Gates
You find the and, or, nand and nor gates, in 2, 3 and 4-input versions, plus xor2 and xnor2. The semantic is obvious.
More Complex Combinatorial Gates
This collection will be kept to a minimum. So far, the xor2 and xnor2, and three composite gates: the 2-wide-2 AND-4 input AND-OR-inverter, also known as a22o2i, its dual o22a2i, and the a21o2i.
This collection will be kept to a minimum . So far, the xor2 and xnor2, and three composite gates: the 2-wide-2 AND-4 input AND-OR-inverter, also known as a22o2i, its dual o22a2i, and the a21o2i.
Input loads are all unit loads.
Sizes: xor2=xnor2=60m, a22o2i=o22a2i=50m, a21o2i=40m.
Output drives: 1/2 for all those cells.
Flip-flops
The only cell which can hold a bit of state is ff, a simple edge-triggered flip-flop with an input, a clock, and complementary outputs.
The clock is internally inverted and buffered; the load on D and CK is one unit load. Both outputs have a unit drive. The size of ff is currently 130m (*).
There is now a version of the flip-flop call ffEn with data enable which takes additional inputs en and nEn. The size of ffEn is currently 140m (*), subtantially smaller than a flip-flop with a 2-input multiplexer. This cell is used to make registers, counters and shift registers.
3. Macros
Macros are simply a convenience for the user: they implement common functions using the basic standard cells gates mentionned above. As any library, this collection of macros cannot fulfill any designer's dream, and in fact it will be kept to a minimum size to simplify maintenance. Our DA system is sufficiently open and extensible that it is staightforward with some drawing and coding to produce any desired macro. When a designer needs a macro, the right thing to do is to implement it himself, and then check if it would benefit others if the macro was incorporated in the library.
All sequential elements (register, counter, shift register) change state on the rising edge of the clock. All inputs are synchronous.
Whenever applicable, the parameters have the following names: b is the number of bits in a word, n is the number of inputs, and v is a value, usually a signed integer.
The default value b𡤀 is illegal and is used to detect icons missing a parameter specification. b<0 is of course illegal, since b is a NAT. One-bit macros (b=1) may sometimes be meaningful, but they are usually a pain because their public contain structured wires with one element, which is not the same as atomic wires. Special cases have been made for the multiplexers, and upon request, I might hack more special cases.
Buffers
An inverting buffer of drive d is equivalent to d inverters in parallel.
Simple n-inputs gates
The and, or, nand and nor gates come in n-input version.
For n=0, the system complains. For n=1, the system also complains, though this might change (*). For n=2, 3, 4 you get one of the standard cells mentionned above. For n>4, the following substitutions are used for the divide and conquer operation:
and -> nor2[nand]
nand -> nand2[and]
or -> nand2[nor]
nor -> nor2[or]
For example, nor[7]=nor2[or[4], or[3]].
Flip-flops with options
The ordinary flip-flop comes with several options: reset, preset, both, and enable.
All these signals are synchronous. Reset has precedence over preset and enable.
Registers
Registers are made of a sequence of flip-flops and come in three options: simple, with enable, and with enable and reset.
Reset overrides enable.
TristateBuffer
Output is high impedance if enable is low, follows or complements the inputs if enable is high. There is an inverting version and a non-inverting one.
SC: The inverting buffer is a sequence of tstDriver with a single inverter to provide the complementary enable signal. Similarly, the non-inverting buffer uses a sequence of b inverters to first invert the inputs.
Adder[b]
Well, it adds. So far, only a ripple carry version is available. It is implemented as a sequence of oneBitAdder.sch, courtesy of Alfred Permuy.
A version with full-CLA will follow (*).
Constant[b, v], Comparator[b] and EqConstant[b, v]
The output of the constant is constantly driven to a fixed b-bit value v. It is legal to specify a size larger than 32 bits as long as the value fits on 32 bits (temporary restriction *). The value is sign-extended to fill-up the b-bit word. Two's complement arithmetic is used, so [b=3, v=-1] is equivalent to [b=3, v=7].
The comparator checks whether two b-bit inputs are bit-wise equal. The constant comparator checks whether the b-bit input is equal to a specified constant v.
The constant is implemented as a bunch of wires connecting to Vdd and Gnd.
The comparator uses one xnor2 gate per pair of input bit, and the b resulting bits are run through a b-input and gate.
The comparator with a constant can be viewed as a one-output decoder: the inputs (inverted or not) are run through a b-input nor gate.
Multiplexers[n, b]
There are really a lot of multiplexers, four families exactly: encoded versus decoded select lines, and 1-bit or b-bit (bus) versions. In addition, special icons (and sometimes different implementations) are provided for 2, (3) and 4 inputs. The number of inputs is denoted by n, and the size of the buses is b.
Decoded muxes all have n select lines and n inputs. The generic 1-bit n-input mux is made of n tristate drivers followed by a single inverter. The b-bit version is obtained by replicating b times the 1-bit version and adding suitable buffers (*) on the select lines. Special cases for n=2 (complex gate a22o2i followed by an inverter), and n=3, 4 (two levels of nand gates).
At most one select line must be high in order to select an input. The usual convention of numbering wires applies and select line
i selects the
i-th input. Out of this envelop, the value of the output depends on the implementation, and no assumption should be made; however, for curious types, the
current implementation is:
All select lines low for n=2, 3, 4 => output is driven to all lows,
All select lines low for n>4 => output is impredictible (tristate off followed by an inverter),
More than one select line high for n=2, 3, 4 => output is the bitwise OR of selected inputs,
More than one select line high for n>4 => output is impredictible (conflicting drivers, static current).
Encoded muxes have a select line with enough bits to encode the number of inputs. If the value on the select line is i, with 0 d i < n, then the i-th data input is selected. Providing a value higher than n (typically i=4 on a 3-input mux) has similar consequences as setting all select lines to low on a decoded mux.
Think of encoded muxes as decoded muxes with a decoder attached on the select line. The decoder obviously takes up space and time, and whenever possible, a decoded mux should be used. Exceptions for n=2, 3, 4 in the 1-bit version: the implementation combines the decoder and the mux in two levels of nands.
There exists an ambiguity for 2-input muxes: since one bit is enough to select among two inputs, is the select line an atomic wire or a composite wire with only one element? It depends. The rule is that if you use explicitely the 2-input icon, then for convenience it is an atomic wire; if you use the generic icon and set n𡤂, then it is a composite wire with one element. This allows parametrized schematics to use muxes with any number of inputs without making a special case for n=2.
Decoder[a, s]
A decoder inputs an a-bit Address and outputs an s-bit Select. If s is not specified, the default is s=2a. If specified, s must be in (0..2a], One version uses an enable line which, when low, forces Select to all lows.
Select expresses in unary what the address expresses in binary. The address inverters will soon be replaced by buffers of appropriate size (*).
Decoders with no enable are smaller and faster than decoders with enable.
Counter
The up-counter provides three functions: Load, Count, and NoOp. Load has priority over Count. Cin and Cout can be used to chain such counters. Complementary outputs are provided.
The control cell and the counter cell are shown above. The buffers' size is proportional to the counter length. A fast version of this counter with carry look-ahead will follow (*).
ShiftReg
The left-shift-register provides three functions: Load, Shift, and NoOp. Load has priority over Shift. The shift is a left-shift, i.e. toward the msb. Cout is a copy of Output[msb] and Cin will be latched as lsb on the next clock edge. Complementary outputs are provided.
The buffers' size is proportional to the shift-register length (*).
4. Standard generators
Generalities
Standard generators are needed for such things as RAMs, for which a standard cell implementation would be disastrous. The standard generator produces a block which can be assembled with other blocks (e.g. standard cells blocks, custom blocks, pads, ...).
Dual-ported Static RAM
The 2-ported RAM has been designed to provide a reasonably dense layout but also a very simple timing. The read and write ports are totally independent. We give here the timing for a 128 by 128 bits RAM (*). Times given in brakets are just estimates.
Read: The read cycle uses a positive precharge signal. Precharge must be asserted for at least [10ns]. The read address must be stable at least [5ns] before the end of precharge, and remain stable for [5ns] after the end of precharge. The data out is valid [5ns] after the end of prechage and remain so until precharge is asserted or until [5ns] after the address changes. If precharge is not asserted in a read cycle, the read takes up to [30ns].
Write: The write cycle uses a positive enable write (enW) signal which must be asserted for at least [10ns]. The data in must be stable at least [5ns] before the end of enW, and remain stable for [5ns] after the end of enW. The write address must be stable at least [5ns] before the beginning of enW, and remain stable for [5ns] after the end of enW. The write address may be changed only when enW is not asserted.
Fifo
The FIFO is made up of two parts: a fifo control block, standard block made of standard cells, and a dual-ported ram (*).
Reset has precedence over Load and UnLoad. Full means n-1 words in the fifo. NF (nearly full) means that there are nbFreeNF words left before the fifo is full. DataAv means the fifo is not empty.
Layout: a mixture of standard cells (counter) and generator (dual-ported RAM).