LogicCounterImpl.mesa
Copyright © 1986 by Xerox Corporation. All rights reserved.
Last Edited by: Louis Monier January 8, 1987 1:45:05 pm PST
Barth, October 22, 1986 11:48:51 am PDT
DIRECTORY CoreCreate, CoreOps, Logic, LogicUtils, Static, Sisyph;
LogicCounterImpl: CEDAR PROGRAM
IMPORTS CoreCreate, CoreOps, Logic, LogicUtils, Static, Sisyph
EXPORTS Logic
= BEGIN OPEN Logic, CoreCreate;
Counter
CounterName: ROPE = "Counter";
Counter: PUBLIC PROC [b: NAT] RETURNS [ct: CellType] = {
counter1B: CellType ← LogicUtils.Extract["counter1B.sch", TRUE]; -- designed by Alfred
insts: CellInstances ← NIL;
IF b=0 THEN LogicUtils.Error["Please provide the number of bits for the counter"];
IF b=1 THEN LogicUtils.Error["Sorry, but a counter must have more than one bit"];
FOR i: NAT IN [0..b) DO
insts ← CONS[
Instance[counter1B,
["dataIn", Index["Input", i]], ["Output", Index["Output", i]],
["carryIn", IF i=b-1 THEN "Cin" ELSE Index["carry", i]],
["carryOut", IF i=0 THEN "Cout" ELSE Index["carry", i-1]],
["nCount", "s1"], ["LoadOrDown", "s0"]],
insts];
ENDLOOP;
ct ← Cell[
name: CounterName,
public: Wires["Vdd", "Gnd", "s0", "s1", "Cin", "Cout", "CK", Seq["Input", b], Seq["Output", b]],
onlyInternal: Wires[Seq["carry", b-1]],
instances: insts];
};
CounterUp
CounterUpName: ROPE = "CounterUp";
CounterUp: PUBLIC PROC [b: NAT] RETURNS [ct: CellType] = {
ctCell: CellType ← LogicUtils.Extract["counterUp1B.sch", TRUE];
ctCtrl: CellType;
insts: CellInstances;
input, output, nOutput, carry, cout: Wire;
IF b=0 THEN LogicUtils.Error["Please provide the number of bits for the up counter"];
IF b=1 THEN LogicUtils.Error["Sorry, but a counter must have more than one bit"];
Sisyph.Store[LogicUtils.cx, "publicD", NEW[NAT←IF b<4 THEN 1 ELSE b/4]];
ctCtrl ← LogicUtils.Extract["counterUp1BCtrl.sch"];
insts ← LIST[Instance[ctCtrl]];
input ← Seq["Input", b];
output ← Seq["Output", b];
nOutput ← Seq["nOutput", b];
carry ← Seq["carry", b];
cout ← CoreOps.SetShortWireName[carry[0], "Cout"];
FOR i: NAT IN [0..b) DO
insts ← CONS[
Instance[ctCell,
["Q", output[i]],
["nQ", nOutput[i]],
["input", input[i]],
["carryIn", IF i=b-1 THEN "Cin" ELSE carry[i+1]],
["carryOut", carry[i]],
["load", "load"], ["count", "count"], ["en", "en"], ["nEn", "nEn"], ["CK", "CK"]],
insts];
ENDLOOP;
ct ← Cell[
name: CounterUpName,
public: Wires["Vdd", "Gnd", "CK", "Load", "Count", "Cin", cout, input, output, nOutput],
onlyInternal: Wires["load", "count", "en", "nEn", carry ],
instances: insts];
};
TestCounterUp: PROC [b: NAT] RETURNS [ct: CellType] = {
ctCell: CellType ← LogicUtils.SCBlock[LogicUtils.Extract["counterUp1B.sch", TRUE]];
ctCtrl: CellType;
insts: CellInstances;
input, output, nOutput, carry, cout: Wire;
IF b=0 THEN LogicUtils.Error["Please provide the number of bits for the up counter"];
IF b=1 THEN LogicUtils.Error["Sorry, but a counter must have more than one bit"];
Sisyph.Store[LogicUtils.cx, "publicD", NEW[NAT←IF b<4 THEN 1 ELSE b/4]];
ctCtrl ← LogicUtils.Extract["counterUp1BCtrl.sch"];
insts ← LIST[Instance[ctCtrl]];
input ← Seq["Input", b];
output ← Seq["Output", b];
nOutput ← Seq["nOutput", b];
carry ← Seq["carry", b];
cout ← CoreOps.SetShortWireName[carry[0], "Cout"];
FOR i: NAT IN [0..b) DO
insts ← CONS[
Instance[ctCell,
["Q", output[i]],
["nQ", nOutput[i]],
["input", input[i]],
["carryIn", IF i=b-1 THEN "Cin" ELSE carry[i+1]],
["carryOut", carry[i]],
["load", "load"], ["count", "count"], ["freeze", "freeze"], ["CK", "CK"]],
insts];
ENDLOOP;
ct ← Cell[
name: CounterUpName,
public: Wires["Vdd", "Gnd", "CK", "Load", "Count", "Cin", cout, input, output, nOutput],
onlyInternal: Wires["load", "count", "freeze", carry ],
instances: insts];
};
Left-ShiftReg
ShRegName: ROPE = "ShReg";
ShRegLeft: PUBLIC PROC [b: NAT] RETURNS [ct: CellType] = {
shCell: CellType ← LogicUtils.Extract["shReg1B.sch", TRUE];
shCtrl: CellType;
insts: CellInstances;
output, outMSB: Wire;
IF b=0 THEN LogicUtils.Error["Please provide the number of bits for the shift register"];
IF b=1 THEN LogicUtils.Error["A shift register must have more than one bit"];
Sisyph.Store[LogicUtils.cx, "publicD", NEW[NAT←IF b<4 THEN 1 ELSE b/4]];
shCtrl ← LogicUtils.Extract["shRegCtrl.sch"];
insts ← LIST[Instance[shCtrl]];
output ← Seq["Output", b];
outMSB ← CoreOps.SetShortWireName[output[0], "outMSB"];
FOR i: NAT IN [0..b) DO
insts ← CONS[
Instance[shCell,
["Q", output[i]],
["prev", IF i=b-1 THEN "inLSB" ELSE output[i+1]],
["nQ", Index["nOutput", i]],
["input", Index["Input", i]],
["load", "load"], ["shift", "shift"], ["en", "en"], ["nEn", "nEn"], ["CK", "CK"]],
insts];
ENDLOOP;
ct ← Cell[
name: ShiftRegName,
public: Wires["Vdd", "Gnd", "CK", "Load", "Shift", "inLSB", outMSB, Seq["Input", b], output, Seq["nOutput", b]],
onlyInternal: Wires["load", "shift", "en", "nEn"],
instances: insts];
};
ShiftReg
ShiftRegName: ROPE = "ShiftReg";
ShiftReg: PUBLIC PROC [b: NAT] RETURNS [ct: CellType] = {
ff: CellType ← FF4[];
insts: CellInstances ← NIL;
fake: Wire ← Static.UnconnectedOK[Seq["fake", b]];
IF b=0 THEN LogicUtils.Error["Please provide the number of bits for the shift register"];
IF b=1 THEN LogicUtils.Error["A shift register must have more than one bit"];
FOR i: NAT IN [0..b) DO
insts ← CONS[
Instance[ff,
["D0", IF i=0 THEN "inR" ELSE Index["Output", i-1]],
["D1", IF i=b-1 THEN "inL" ELSE Index["Output", i+1]],
["D2", Index["Output", i]],
["D3", Index["Input", i]],
["Q", Index["Output", i]],
["NQ", Index[fake, i]],
["s0", "s0"], ["s1", "s0"], ["s2", "s1"]],
insts];
ENDLOOP;
ct ← Cell[
name: ShiftRegName,
public: Wires["Vdd", "Gnd", "s0", "s1", "CK", "inL", "inR", Seq["Input", b], Seq["Output", b]],
onlyInternal: Wires[fake],
instances: insts];
};
END.
[] ← Counter[2];
[] ← ShiftReg[2];