DIRECTORY CD USING [Design], Core USING [CellClass, CellType, Properties, Wire, Wires], Boole USING [Expression], CoreCreate USING [PA, WR], Rope USING [ROPE], Sisyph USING [Context]; TrueAlps: CEDAR DEFINITIONS = BEGIN Expression: TYPE = Boole.Expression; ROPE: TYPE = Rope.ROPE; CellType: TYPE = Core.CellType; Properties: TYPE = Core.Properties; Wire: TYPE = Core.Wire; Wires: TYPE = Core.Wires; WR: TYPE = CoreCreate.WR; PA: TYPE = CoreCreate.PA; inputXmeansX: BOOL; InputRec: TYPE = RECORD [ input: WR, driver: CellType, pas: LIST OF PA _ NIL ]; OutputRec: TYPE = RECORD [ output: WR, expr: Expression, driver: CellType, pas: LIST OF PA _ NIL ]; Inputs: TYPE = LIST OF InputRec; Outputs: TYPE = LIST OF OutputRec; trueAlpsClass: Core.CellClass; cellLibrary: CD.Design; -- read from TrueAlps.dale cx: Sisyph.Context; -- the Sysiph context derived form it AlpsCell: PROC [public: Wire, inputs: Inputs, outputs: Outputs, name: ROPE _ NIL, props: Properties _ NIL] RETURNS [recordCell: CellType]; WireVar: PROC [public: Wire, wr: WR] RETURNS [expr: Expression]; EqualInt: PROC [public: Wire, wr: WR, int: INT] RETURNS [expr: Expression]; Size: PROC [vars: LIST OF ROPE, expr: Expression] RETURNS [size: INT _ 0]; END. 4TrueAlps.mesa Copyright c 1986 by Xerox Corporation. All rights reversed. Created by Bertrand Serlet June 22, 1986 10:32:36 pm PDT Bertrand Serlet June 22, 1986 10:59:36 pm PDT Common Types Connection with CoreCreate The public of driver must contain 3 atomic wires named "Input", "Output" and "OutputNot". The layout of the driver must be a cell of TrueAlps. Inter driver communication (such as "Gnd" or "Vdd") should not appear in pas. In effect, pas should only contain the input-dependent bindings (such as "Clock", "PhiA"). The public of driver must contain 2 atomic wires named "Input" and "Output". The layout of the driver must be a cell of TrueAlps. Inter driver communication (such as "Gnd" or "Vdd") should not appear in pas. In effect, pas should only contain the output-dependent bindings (such as "Clock", "PhiA"). Objects of class alpsCellClass know how to simulate themselves with Rosemary, and how to generate their layouts. The returned recordCell contains all the given drivers as instances, plus a bunch of instances of class trueAlpsClass, that are simulable with Rosemary. Public should contain two wires called "Gnd" and "Vdd" that are the power supply. Order of inputs gives the order of the input variables (left to right). Order of outputs gives the order of the outputs (bottom to top). Returns the expression that wr expresses Returns the expression so that the atomic wires of wr express in binary the quantity int. Wr must be a real Core.Wire (WR is there only for user convenience, but a ROPE does not make sense). Implementors goodies ΚΌ˜– "Cedar" stylešœ™Jšœ Οmœ1™