
    <<JMHCell.mesa>>
        <<Copyright Ó 1985, 1986, 1987 by Xerox Corporation.  All rights reserved.>>
        <<Bertrand Serlet March 3, 1987 1:05:52 am PST>>

    DIRECTORY Boole, BooleCore, Core, CoreCreate, CoreOps, PW, PWCore;

    JMHCell: CEDAR PROGRAM
        IMPORTS Boole, BooleCore, CoreCreate, CoreOps, PW, PWCore = 
        BEGIN OPEN Boole; 

    ByteType: INT=0; -- random
    LongType: INT = 0; -- random
    Create: PROC RETURNS [cellType: Core.CellType] = {
        inputs: BooleCore.Inputs _ NIL;
        outputs: BooleCore.Outputs _ NIL;
        inv: Core.CellType _ BooleCore.GetCellLibraryCell["InputDriver"];
        out: Core.CellType _ BooleCore.GetCellLibraryCell["OutputDriver"];
        pas: LIST OF CoreCreate.PA _ LIST[["VRef", "VRef"]];

        gateRD: Core.Wire = CoreOps.CreateWire[name: "gateRD"];
        gateWR: Core.Wire = CoreOps.CreateWire[name: "gateWR"];
        RdCmd: Core.Wire = CoreOps.CreateWire[name: "RdCmd"];
        IORange: Core.Wire = CoreOps.CreateWire[name: "IORange"];
        IsCy2: Core.Wire = CoreOps.CreateWire[name: "IsCy2"];
        IOType: Core.Wire = CoreCreate.Seq["IOType", 2];
        MType: Core.Wire = CoreCreate.Seq["MType", 4];
        A1: Core.Wire = CoreOps.CreateWire[name: "A1"];
        A0: Core.Wire = CoreOps.CreateWire[name: "A0"];

        IORangeRdCmd: Core.Wire = CoreCreate.Wires[IORange, RdCmd];
        IOByte: Expression = Nor[Not[IORange], IOType[0], IOType[1]];
        nIOInta: Expression = Nand[IORange, IOType[0], IOType[1]];

        inputs _ CONS [[input: "gateRD", driver: inv], inputs];
        inputs _ CONS [[input: "gateWR", driver: inv], inputs];
        inputs _ CONS [[input: "RdCmd", driver: inv], inputs];
        inputs _ CONS [[input: "IORange", driver: inv], inputs];
        inputs _ CONS [[input: "IsCy2", driver: inv], inputs];
        inputs _ CONS [[input: "IOType[0]", driver: inv], inputs];
        inputs _ CONS [[input: "IOType[1]", driver: inv], inputs];
        inputs _ CONS [[input: "MType[0]", driver: inv], inputs];
        inputs _ CONS [[input: "MType[1]", driver: inv], inputs];
        inputs _ CONS [[input: "MType[2]", driver: inv], inputs];
        inputs _ CONS [[input: "MType[3]", driver: inv], inputs];
        inputs _ CONS [[input: "A1", driver: inv], inputs];
        inputs _ CONS [[input: "A0", driver: inv], inputs];

        outputs _ CONS [[
            output: "nDEN", driver: out, pas: pas, 
            expr: Xor[Nand[RdCmd, gateRD], Nand[gateWR, Not[RdCmd]]]
            ], outputs];
        outputs _ CONS [[
            output: "nDTR", driver: out, pas: pas, 
            expr: RdCmd
            ], outputs];
        outputs _ CONS [[
            output: "WR", driver: out, pas: pas, 
            expr: And[BooleCore.EqualInt[IORangeRdCmd, 0], gateWR]
            ], outputs];
        outputs _ CONS [[
            output: "RD", driver: out, pas: pas, 
            expr: And[BooleCore.EqualInt[IORangeRdCmd, 1], gateRD]
            ], outputs];
        outputs _ CONS [[
            output: "IOW", driver: out, pas: pas, 
            expr: And[BooleCore.EqualInt[IORangeRdCmd, 2], gateWR]
            ], outputs];
        outputs _ CONS [[
            output: "IOR", driver: out, pas: pas, 
            expr: And[BooleCore.EqualInt[IORangeRdCmd, 3], gateRD]
            ], outputs];
        outputs _ CONS [[
            output: "INTA", driver: out, pas: pas, 
            expr: And[Not[gateRD], nIOInta]
            ], outputs];
        outputs _ CONS [[
            output: "EnB3", driver: out, pas: pas, 
            expr: Nor[Not[gateRD], And[IsCy2, nIOInta]]
            ], outputs];
        outputs _ CONS [[
            output: "EnB2", driver: out, pas: pas, 
            expr: Nor[Not[nIOInta], IOByte, IsCy2, Not[gateRD]]
            ], outputs];
        outputs _ CONS [[
            output: "EnB01", driver: out, pas: pas, 
            expr: Nor[Not[nIOInta], Not[IsCy2], Not[gateRD]]
            ], outputs];
        outputs _ CONS [[
            output: "A1Out", driver: out, pas: pas, 
            expr: Not[Xor[IsCy2, A1]]
            ], outputs];
        outputs _ CONS [[
            output: "nSwap", driver: out, pas: pas, 
            expr: Nand[A0, nIOInta]
            ], outputs];
        outputs _ CONS [[
            output: "A0Out", driver: out, pas: pas, 
            expr: And[A0, Nor[IOByte], BooleCore.EqualInt[MType, ByteType]]
            ], outputs];
        outputs _ CONS [[
            output: "nBHEOut", driver: out, pas: pas, 
            expr: And[Not[A0], Nor[IOByte], BooleCore.EqualInt[MType, ByteType]]
            ], outputs];
        outputs _ CONS [[
            output: "X2Cy", driver: out, pas: pas, 
            expr: Or[BooleCore.EqualInt[MType, ByteType], And[IOType[0], IORange]]
            ], outputs];

        <<-- Generate the block Alps>>
        cellType _ BooleCore.AlpsCell[
            name: "MakeJMHCell", 
            public: CoreCreate.WireList[LIST [
                gateRD, gateWR, RdCmd, IORange, IsCy2, IOType, MType, A1, A0, 
                "nDEN", "nDTR", "WR", "RD", "IOW", "IOR", "INTA", "EnB3", "EnB2", "EnB01", "A1Out", "nSwap", "A0Out", "nBHEOut", "X2Cy", 
                "Vdd", "Gnd", "VRef"
                ]], 
            inputs: inputs, outputs: outputs
            ];
        };

    MakeJMHCell: PW.UserProc = {RETURN [PWCore.Layout[Create[]]]};

    PW.Register[MakeJMHCell, "MakeJMHCell"];

    END.