Create:
PROC
RETURNS [cellType: Core.CellType] = {
inputs: BooleCore.Inputs ← NIL;
outputs: BooleCore.Outputs ← NIL;
inv: Core.CellType ← BooleCore.GetCellLibraryCell["InputDriver"];
out: Core.CellType ← BooleCore.GetCellLibraryCell["OutputDriver"];
pas: LIST OF CoreCreate.PA ← LIST[["VRef", "VRef"]];
gateRD: Core.Wire = CoreOps.CreateWire[name: "gateRD"];
gateWR: Core.Wire = CoreOps.CreateWire[name: "gateWR"];
RdCmd: Core.Wire = CoreOps.CreateWire[name: "RdCmd"];
IORange: Core.Wire = CoreOps.CreateWire[name: "IORange"];
IsCy2: Core.Wire = CoreOps.CreateWire[name: "IsCy2"];
IOType: Core.Wire = CoreCreate.Seq["IOType", 2];
MType: Core.Wire = CoreCreate.Seq["MType", 4];
A1: Core.Wire = CoreOps.CreateWire[name: "A1"];
A0: Core.Wire = CoreOps.CreateWire[name: "A0"];
IORangeRdCmd: Core.Wire = CoreCreate.Wires[IORange, RdCmd];
IOByte: Expression = Nor[Not[IORange], IOType[0], IOType[1]];
nIOInta: Expression = Nand[IORange, IOType[0], IOType[1]];
inputs ← CONS [[input: "gateRD", driver: inv], inputs];
inputs ← CONS [[input: "gateWR", driver: inv], inputs];
inputs ← CONS [[input: "RdCmd", driver: inv], inputs];
inputs ← CONS [[input: "IORange", driver: inv], inputs];
inputs ← CONS [[input: "IsCy2", driver: inv], inputs];
inputs ← CONS [[input: "IOType[0]", driver: inv], inputs];
inputs ← CONS [[input: "IOType[1]", driver: inv], inputs];
inputs ← CONS [[input: "MType[0]", driver: inv], inputs];
inputs ← CONS [[input: "MType[1]", driver: inv], inputs];
inputs ← CONS [[input: "MType[2]", driver: inv], inputs];
inputs ← CONS [[input: "MType[3]", driver: inv], inputs];
inputs ← CONS [[input: "A1", driver: inv], inputs];
inputs ← CONS [[input: "A0", driver: inv], inputs];
outputs ←
CONS [[
output: "nDEN", driver: out, pas: pas,
expr: Xor[Nand[RdCmd, gateRD], Nand[gateWR, Not[RdCmd]]]
], outputs];
outputs ←
CONS [[
output: "nDTR", driver: out, pas: pas,
expr: RdCmd
], outputs];
outputs ←
CONS [[
output: "WR", driver: out, pas: pas,
expr: And[BooleCore.EqualInt[IORangeRdCmd, 0], gateWR]
], outputs];
outputs ←
CONS [[
output: "RD", driver: out, pas: pas,
expr: And[BooleCore.EqualInt[IORangeRdCmd, 1], gateRD]
], outputs];
outputs ←
CONS [[
output: "IOW", driver: out, pas: pas,
expr: And[BooleCore.EqualInt[IORangeRdCmd, 2], gateWR]
], outputs];
outputs ←
CONS [[
output: "IOR", driver: out, pas: pas,
expr: And[BooleCore.EqualInt[IORangeRdCmd, 3], gateRD]
], outputs];
outputs ←
CONS [[
output: "INTA", driver: out, pas: pas,
expr: And[Not[gateRD], nIOInta]
], outputs];
outputs ←
CONS [[
output: "EnB3", driver: out, pas: pas,
expr: Nor[Not[gateRD], And[IsCy2, nIOInta]]
], outputs];
outputs ←
CONS [[
output: "EnB2", driver: out, pas: pas,
expr: Nor[Not[nIOInta], IOByte, IsCy2, Not[gateRD]]
], outputs];
outputs ←
CONS [[
output: "EnB01", driver: out, pas: pas,
expr: Nor[Not[nIOInta], Not[IsCy2], Not[gateRD]]
], outputs];
outputs ←
CONS [[
output: "A1Out", driver: out, pas: pas,
expr: Not[Xor[IsCy2, A1]]
], outputs];
outputs ←
CONS [[
output: "nSwap", driver: out, pas: pas,
expr: Nand[A0, nIOInta]
], outputs];
outputs ←
CONS [[
output: "A0Out", driver: out, pas: pas,
expr: And[A0, Nor[IOByte], BooleCore.EqualInt[MType, ByteType]]
], outputs];
outputs ←
CONS [[
output: "nBHEOut", driver: out, pas: pas,
expr: And[Not[A0], Nor[IOByte], BooleCore.EqualInt[MType, ByteType]]
], outputs];
outputs ←
CONS [[
output: "X2Cy", driver: out, pas: pas,
expr: Or[BooleCore.EqualInt[MType, ByteType], And[IOType[0], IORange]]
], outputs];
-- Generate the block Alps
cellType ← BooleCore.AlpsCell[
name: "MakeJMHCell",
public: CoreCreate.WireList[
LIST [
gateRD, gateWR, RdCmd, IORange, IsCy2, IOType, MType, A1, A0,
"nDEN", "nDTR", "WR", "RD", "IOW", "IOR", "INTA", "EnB3", "EnB2", "EnB01", "A1Out", "nSwap", "A0Out", "nBHEOut", "X2Cy",
"Vdd", "Gnd", "VRef"
]],
inputs: inputs, outputs: outputs
];
};