
    <<BooleTest.mesa>>
    <<Copyright © 1985, 1986 by Xerox Corporation.  All rights reversed.>>
    <<Created by Bertrand Serlet July 31, 1985 3:03:17 pm PDT>>
    <<Last edited by Bertrand Serlet June 17, 1986 6:01:16 pm PDT>>
        <<Barth, June 13, 1986 3:37:52 pm PDT>>
        <<Louis Monier April 8, 1986 11:56:33 am PST>>
        <<Last Edited by: Louis Monier August 8, 1986 11:39:41 am PDT>>
        <<>>
    DIRECTORY  
        Boole, BooleCore, BooleCoreImpl, CD, CDProperties, Core, CoreClasses, CoreCreate, CoreOps, CoreProperties, PW, PWCore, Rope, 
        Rosemary, RosemaryUser, Ports, Sisyph;

    BooleTest: CEDAR PROGRAM
        IMPORTS Boole, BooleCore, CDProperties, CoreCreate, CoreOps, CoreProperties, PW, PWCore, Rosemary, RosemaryUser, Ports, Sisyph
        SHARES BooleCoreImpl = 
        BEGIN OPEN Boole, BooleCore;
<<Basic Test>>
Decoder: PUBLIC PROC [] RETURNS [result: Expression] = {
pBar: Expression _ true;
gBar: Expression _ true;
a, b, c, d: Expression;
plus, or, and, xor: Expression;

a _ Var["a"]; b _ Var["b"]; c _ Var["c"]; d _ Var["d"];
plus _ And[c, d]; 
xor _ And[Not[c], d]; 
and _ And[c, Not[d]];
or _ And[Not[c], Not[d]];

pBar _ If[plus, Xor[a, Not[b]], pBar];
gBar _ If[plus, Or[Not[a], Not[b]], gBar];

pBar _ If[or, Nor[a, b], pBar];
pBar _ If[and, Not[And[a, b]], pBar];
pBar _ If[xor, Xor[a, Not[b]], pBar];

result _ And[gBar, pBar];

};
<<Test of BooleCore>>
    design: CD.Design _ BooleCore.cellLibrary;
    cx: Sisyph.Context _ BooleCore.cx;

    AlpsExtract: PROC [name: ROPE] RETURNS [cellType: CellType] ~ {
        cellType _ Sisyph.ExtractSchematicByName[name: name, cx: cx];
        PWCore.SetGet[cellType, design];
        };

DecoderCellType: PUBLIC PROC [] RETURNS [recordCell: CellType] = {
inputDriver: CellType _ AlpsExtract["InputDriver.sch"];
outputDriver: CellType _ AlpsExtract["ClockedOutputDriver.sch"];
recordCell _ AlpsCell[
public: CoreCreate.Wires["a", "b", "c", "d", "r", "ab", "Gnd", "Vdd", "phiA", "phiB", "VRef"], 
inputs: LIST [["a", inputDriver], ["b", inputDriver], ["c", inputDriver], ["d", inputDriver]], 
outputs: LIST [
["r", Decoder[], outputDriver, LIST [["Clock", "phiA"], ["VRef", "VRef"]]],
["ab", And[Var["a"], Var["b"]], outputDriver, LIST [["Clock", "phiB"], ["VRef", "VRef"]]]
],
props: CoreProperties.Props[[$ContactPolyMetal2, NEW [INT _ 3]]]
];
};

    a, b, c, d, r, ab, Gnd, Vdd, phiA, phiB, VRef: NAT;

    RopeLevel: TYPE = RECORD [rope: ROPE, level: Ports.Level];
    Ev: PROC [expr: Expression, rls: LIST OF RopeLevel] RETURNS [Expression] = {
        SELECT TRUE FROM
            rls=NIL    => RETURN [expr];
            rls.first.level=X => RETURN [Ev[expr, rls.rest]];
            rls.first.level=H => RETURN [Ev[Boole.Eval[rls.first.rope, expr].whenTrue, rls.rest]];
            rls.first.level=L => RETURN [Ev[Boole.Eval[rls.first.rope, expr].whenFalse, rls.rest]];
            ENDCASE        => ERROR;
        };

    AlpsTest: RosemaryUser.TestProc = {
    rexpr: Expression _ Decoder[];
    abexpr: Expression _ And[Var["a"], Var["b"]];
    FOR av: Ports.Level IN Ports.Level DO
    p[a].l _ av;
    FOR bv: Ports.Level IN Ports.Level DO
    p[b].l _ bv;
    FOR cv: Ports.Level IN Ports.Level DO
    p[c].l _ cv;
    FOR dv: Ports.Level IN Ports.Level DO
    p[d].l _ dv;
    p[r].l _ SELECT Ev[rexpr, LIST[["a", av], ["b", bv], ["c", cv], ["d", dv]]] FROM
    Boole.true    => H,
    Boole.false    => L,
    ENDCASE        => X;
    p[ab].l _ SELECT Ev[abexpr, LIST[["a", av], ["b", bv], ["c", cv], ["d", dv]]] FROM
    Boole.true    => H,
    Boole.false    => L,
    ENDCASE        => X;
    Eval[];
    ENDLOOP;
    ENDLOOP;
    ENDLOOP;
    ENDLOOP;
        };

    ExerciseRose: PUBLIC PROC = {
        ct: CellType _ DecoderCellType[];
        public: Wire _ ct.public;
        data: CoreClasses.RecordCellType _ NARROW [ct.data];
        sim: Rosemary.Simulation;
        design: PW.Design;
        a _ CoreOps.GetWireIndex[public, "a"];
        b _ CoreOps.GetWireIndex[public, "b"];
        c _ CoreOps.GetWireIndex[public, "c"];
        d _ CoreOps.GetWireIndex[public, "d"];
        r _ CoreOps.GetWireIndex[public, "r"];
        ab _ CoreOps.GetWireIndex[public, "ab"];
        Gnd _ CoreOps.GetWireIndex[public, "Gnd"];
        Vdd _ CoreOps.GetWireIndex[public, "Vdd"];
        phiA _ CoreOps.GetWireIndex[public, "phiA"];
        phiB _ CoreOps.GetWireIndex[public, "phiB"];
        VRef _ CoreOps.GetWireIndex[public, "VRef"];
        [] _ Rosemary.SetFixedWire[public[Vdd], H];
        [] _ Rosemary.SetFixedWire[public[Gnd], L];
        [] _ Rosemary.SetFixedWire[public[phiA], H];
        [] _ Rosemary.SetFixedWire[public[phiB], H];
        [] _ Rosemary.SetFixedWire[public[VRef], H];
        FOR i: NAT IN [0..ct.public.size) DO
            [] _ Ports.InitPort[wire: ct.public[i], levelType: l];
            ENDLOOP;
        [] _ Ports.InitTesterDrive[wire: ct.public[a], initDrive: force];
        [] _ Ports.InitTesterDrive[wire: ct.public[b], initDrive: force];
        [] _ Ports.InitTesterDrive[wire: ct.public[c], initDrive: force];
        [] _ Ports.InitTesterDrive[wire: ct.public[d], initDrive: force];
        [] _ Ports.InitTesterDrive[wire: ct.public[r], initDrive: expect];
        [] _ Ports.InitTesterDrive[wire: ct.public[ab], initDrive: expect];
        sim _ RosemaryUser.TestProcedureViewer[name: "Alps Transistor Tester", cellType: ct, testButtons: LIST["AlpsTest"], displayWires: 
        RosemaryUser.DisplayCellTypePortLeafWires[ct], flatten: TRUE];
        design _ PW.Draw[PWCore.Layout[ct]];
        CDProperties.PutDesignProp[design, $Simulation, sim];
        [] _ RosemaryUser.TestProcedureViewer[name: "Alps Alps Tester", cellType: ct, testButtons: LIST["AlpsTest"], displayWires: 
        RosemaryUser.DisplayCellTypePortLeafWires[ct], flatten: TRUE, cutSets: LIST["AlpsCell"]];
        };

    RosemaryUser.RegisterTestProc["AlpsTest", AlpsTest];

    END.