McCreight, April 2, 1985 6:16:51 pm PST

Sweetsun Chen, September 18, 1985 9:36:43 pm PDT

fet: MosFet[gate, source, drain, bulk |

}; -- NETran

sdExtend default set to 0, dWFact added by McCreight, March 7, 1985 12:41:31 pm PST

sdExtend is added by Ted Williams on July 7, 1983 11:48 AM

It is a guessed value to calculate source and drain capacitance, as suggested by McCreight. Nobody really has a better way.

nt: NETran[gate, source, drain, Gnd |

}; -- ETran

l ← 2, w ← 24, as ← 720, ad ← 720, ps ← 110, pd ← 110, dWFact ← 1] = {

}; -- PETran

pt: PETran[gate, source, drain, Vdd |

}; -- CTran

L ← 4, W ← 2, sourceExtension ← 1, drainExtension ← 1, dWFact ← 1]= {

fet: MosFet[gate, source, drain, Gnd |

}; -- NDTran

lM2 ← 0, wM2 ← 4, aM2 ← 0, pM2 ← 0, -- 2nd layer metal

lM ← 0, wM ← 3, aM ← 0, pM ← 0, -- 1rst layer metal

lP ← 0, wP ← 2, aP ← 0, pP ← 0, -- poly

aG← 0, pG ← 0, -- poly over thin oxide (if transistor unsimulated)

aM2C ← .197E-4pF, pM2C ← .486E-4pF, -- /(uM)^2, /uM, 2nd layer metal to bulk

aMC ← .276E-4pF, pMC ← .496E-4pF, -- 1rst layer metal to bulk

aPC ← .628E-4pF, pPC ← .577E-4pF, -- poly to bulk

aGC ← 11.8e-4pF -- poly over thin oxide

] = {

?: capacitor[n, Gnd] = Lambda*(Lambda*((aM2 + lM2*wM2)*aM2C + (aM + lM*wM)*aMC + (aP + lP*wP)*aPC + aG*aGC) + (pM2 + 2*lM2 + 2*wM2)*pM2C + (pM + 2*lM + 2*wM)*pMC + (pP + 2*lP)*pPC)

}; -- WireCap

lnD ← 0, wnD ← 0, anD ← 0, pnD ← 0, lpD ← 0, wpD ← 0, apD ← 0, ppD ← 0]= {

The 0-bias values are taken from ICL's "Report on Process and Electrical Parameters" by Richard Bruce and John Chen, dated 21 Feb 85. The n+ area and perimeter values in that report are measured, and the p+ area and perimeter values are inherited from I. Bol's MEC "Xerox CMOS Process Specification and Layout Design Rules" memo of February 83.

ndc: Diffusion[n, Gnd |

pdc: Diffusion[n, Gnd |

}; -- DifCap

lM2 ← 0, wM2 ← 4,

lM ← 0, wM ← 3,

lP ← 0, wP ← 2,

lnD ← 0, wnD ← 2,

lpD ← 0, wpD ← 2,

sM2R ← 0.06, -- ohms/square

sMR ← 0.06,

sPR ← 3.5, -- polysilicide

snDR ← 35,

spDR ← 120] = {

R: resistor[nodeA, nodeB] = lM2/wM2*sM2R + lM/wM*sMR + lP/wP*sPR + lnD/wnD*snDR + lpD/wpD*spDR

}; -- WireRes

nM2M ← 0, -- number of parallel 2nd layer metal to 1rst layer metal vias

nMP ← 0, -- number of parallel 1rst layer metal to poly contacts

nMD ← 0, -- number of parallel 1rst layer metal to diffusion contacts

nPD ← 0, -- number of parallel poly to diffusion contacts, butting

cM2MR ← 40, -- ohms/via, 2nd layer metal to 1rst layer

cMPR ← 4, -- ohms/contact, metal-polysilicide

cMDR ← 25, -- ohms/contact, metal-diffusion

cPDR ← 50 -- ohms/contact, poly-diffusion, with metal strap, i.e. butting contact

] = {

R: resistor[nodeA, nodeB] = 1/(nM2M/cM2MR + nMP/cMPR + nMD/cMDR + nPD/cPDR)

}; -- ConRes

aM2 ← 0, pM2 ← 0,

aM ← 0, pM ← 0,

aP ← 0, pP ← 0,

anD ← 0, pnD ← 0,

apD ← 0, ppD ← 0,

aG ← 0, pG ← 0

] = {

wireCap: WireCap [n |

difCap: DifCap [n | anD ← anD, pnD ← pnD, apD ← apD, ppD ← ppD];

}; -- Stray

to cause calculated stray capacitances to agree with Wheeler's microstrip equations for fringing capacitance (Transmission-Line Properties of a Strip on a Dielectric Sheet on a Plane, IEEE Transactions on Microwave Theory and Techniques, vol MTT-25, No. 8, August, 1977, pp. 631-647).

to cause diffusion capacitances to agree with ICL's Report on Process and Electrical Parameters by R. Bruce and J. Chen, 21 Feb 85.

NOTE: The CSIM transistor parameters agree with measured data taken from (CMOS36) Run 120, Wafer 10, DIE=128-127. This data in turn agrees with the nominal n-channel transconductance in ICL's Report, but is near the minimum p-channel transconductance in that report.