DIRECTORY CD,Core,CoreCreate,CoreOps,CoreClasses,IO,PW,Rope,SC,ViewerIO;SCTestPW: CEDAR PROGRAMIMPORTS CD, CoreCreate, CoreOps, PW, SC, ViewerIOSHARES SC =BEGINdebug: BOOLEAN _ FALSE;CreateCore: PROC [] RETURNS [Core.Design, Core.CellType] =BEGINandInst, invInst: CoreClasses.CellInstance;coreDesign: Core.Design _ CoreOps.CreateDesign["SCTestPW"];SCTestPW: Core.CellType _ CoreCreate.CreateRecordCell[coreDesign, "SCTestPW"];nand: Core.CellType _ CoreCreate.CreateRecordCell[coreDesign, "NAND"];inverter: Core.CellType _ CoreCreate.CreateRecordCell[coreDesign, "Inverter"];[] _ CoreCreate.CreatePublicWire[coreDesign, SCTestPW, NIL, LIST["InA", "InB", "Out"]];[] _ CoreCreate.CreatePublicWire[coreDesign, nand, NIL, LIST["InA", "InB", "Out"]];[] _ CoreCreate.CreatePublicWire[coreDesign, inverter, NIL, LIST["In", "Out"]];[] _ CoreCreate.CreateWire[coreDesign, SCTestPW, "NOut"];andInst _ CoreCreate.CreateCellInstance[coreDesign, SCTestPW, nand, "InA: InA, InB: InB, Out: NOut", NIL, "andInst"];invInst _ CoreCreate.CreateCellInstance[coreDesign, SCTestPW, inverter, "In: NOut, Out: Out", NIL, "invInst"];RETURN [coreDesign, SCTestPW];END;DoLayout: PROC [coreDesign: Core.Design, cellType: Core.CellType, cdDesign, libDesign: CD.Design] RETURNS [result: SC.Result _ NIL] =BEGINtechnology: CD.Technology _ CD.FetchTechnology[$cmos];metal: SC.Layer _ CD.FetchLayer[technology, $met];metal2: SC.Layer _ CD.FetchLayer[technology, $met2];rules: SC.DesignRules _ SC.CreateDesignRules[$cmos, metal, metal2, horizontal];IF libDesign # NIL THEN{handle: SC.Handle _ SC.CreateHandle[coreDesign, cellType, cdDesign, libDesign, rules];SC.InitialPlace[handle];SC.GlobalRoute[handle];SC.PlaceImprove[handle, $globalRouting];result _ SC.DetailRoute[handle]};END;WriteCore: PROC [coreDesign: Core.Design, debug: BOOLEAN] =BEGINIF debug THEN {out: IO.STREAM _ ViewerIO.CreateViewerStreams[name: "Core: SCTestPW", viewer: NIL, editedStream: FALSE].out;CoreOps.PrintDesign[coreDesign, out]};END;TestSCTiny: PW.UserProc =BEGINcoreDesign: Core.Design;cellType: Core.CellType;result: SC.Result;libName: Rope.ROPE _"SCTest.dale";libDesign: CD.Design _ PW.OpenDesign[libName];[coreDesign, cellType] _ CreateCore[];WriteCore[coreDesign, debug];result _ DoLayout[coreDesign, cellType, NIL, libDesign];RETURN[result.object];END;PW.Register[TestSCTiny, "TestSCTiny"];END.   Ö  SCTestPW.mesaCopyright c 1985 by Xerox Corporation.  All rights reserved.Last Edited by: Preas, September 5, 1985 10:39:21 am PDTBryan Preas September 5, 1985 10:37:21 am PDTUse with the file SCTestPW.dale to test routing:SC.loadcdread SCTestPW -- NOTE: SCTest.dale must be in the /// directoryrun SCTestPWmiddle click P in the ChipNDale viewerselect the appropriate generatorCreate a Core designCreate a standard cell objectWrite Core to a viewer Ê[  ˜ Jšœ™Jšœ
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