DIRECTORY CD, Core, D2Basic, Rope, Route, RTSets, RTBasic, SC; SCPrivate: CEDAR DEFINITIONS = BEGIN CompClass: TYPE = {other, logic, io, ft}; DegreeOfConnection: TYPE = {full, min, none}; ChanConnect: TYPE = PACKED ARRAY RTSets.RTMdSetRange OF DegreeOfConnection _ ALL[none]; LRSide: TYPE = RTBasic.LRSide; TBSide: TYPE = RTBasic.TBSide; LRSideSet: TYPE = RTSets.RTSmSet -- OF Lrsidetype -- ; SideSet: TYPE = RTSets.RTSmSet -- OF Validside -- ; RowSet: TYPE = RTSets.RTMdSet -- OF Maxrowsr -- ; ChanSet: TYPE = RTSets.RTMdSet -- OF Maxchansr -- ; StructureData: TYPE = REF StructureDataRec; StructureDataRec: TYPE = RECORD [ objects: Objects _ NIL, instances: Instances _ NIL, nets: Nets _ NIL]; LayoutData: TYPE = REF LayoutDataRec; LayoutDataRec: TYPE = RECORD [ totWidth, totHeight: SC.Number _ 0, bpRows: BpRows _ NIL, lgRows: LgRows _ NIL, sideChans: SideChans _ [NIL, NIL], rowChans: RowChans _ NIL, acBuses: AcBuses _ [NIL, NIL], powerBuses: PowerBuses _ [NIL, NIL], layoutParms: LayoutParms, wireSegs: WireSegs _ NIL, wireSegPins: WireSegPins _ NIL, globalRoute: REF ANY _ NIL]; Parms: TYPE = REF ParmsRec; ParmsRec: TYPE = RECORD [ cdDesign, libDesign: CD.Design _ NIL, ftObject, portObject: Object _ NIL]; LayoutParms: TYPE = REF LayoutParmsRec; LayoutParmsRec: TYPE = RECORD [ whichFom: FomType _ wlFom, useMaxRouteExits, useInteriorChanExits: BOOLEAN _ TRUE, numRows: NAT _ 0, rowDirection: SC.Direction _ horizontal, unitsPerLam: SC.Number _ 2, powerName: ARRAY LRSide OF Rope.ROPE]; maxObjects: NAT = 100; maxPinsOnObject: NAT = 100; MaxObjectsSr: TYPE = NAT[1 .. maxObjects]; -- Object definitions ZMaxObjectsSr: TYPE = NAT[0 .. maxObjects]; -- Object definitions Objects: TYPE = REF ObjectsRec; ObjectsRec: TYPE = RECORD [ count: ZMaxObjectsSr _ 0, ob: ARRAY MaxObjectsSr OF Object _ ALL[NIL]]; Object: TYPE = REF ObjectRec; ObjectRec: TYPE = RECORD [ name: Rope.ROPE _ NIL, objectNum: MaxObjectsSr, size, orgin: RTBasic.PQPos _ [0, 0], numPins: NAT _ 0, pins: ObjectPins _ NIL, typeClass: CompClass _ other, numTimesUsed: NAT _ 0, cdOb: CD.Object _ NIL]; ObjectPin: TYPE = REF ObjectPinRec; ObjectPins: TYPE = REF ObjectPinsRec; ObjectPinsRec: TYPE = RECORD [ p: SEQUENCE size: NAT OF ObjectPin]; ObjectPinRec: TYPE = RECORD [ name: Rope.ROPE _ NIL, pinPos: PinPos, cdPin: CD.Instance _ NIL, rect: SC.Rect _ [0, 0, 0, 0], layer: SC.Layer, equivClass: Rope.ROPE _ NIL]; PinPos: TYPE = RECORD [ side: SC.SideOrNone _ none, depth, location: SC.Number _ 0]; maxInstance: NAT = 5000; MaxInstanceSr: TYPE = NAT[1 .. maxInstance]; ZMaxInstanceSr: TYPE = NAT[0 .. maxInstance]; Instance: TYPE = REF InstanceRec; InstanceList: TYPE = LIST OF Instance; Instances: TYPE = REF InstancesRec; InstancesRec: TYPE = RECORD [ count, numIOs, numLogics, numFts: ZMaxInstanceSr _ 0, inst: Insts _ NIL]; Insts: TYPE = REF InstsOb; InstsOb: TYPE = ARRAY MaxInstanceSr OF Instance _ ALL[NIL]; InstanceRec: TYPE = RECORD [ name: Rope.ROPE, instanceNum: MaxInstanceSr, object: Object _ NIL, pinNets: PinNets _ NIL, prePos, curPos, initPos, fnlPos: ZMaxPosSr _ 0, preOrien, curOrien, initOrien, fnlOrien: OrientationOrNone _ 0, offset: SC.Number _ 0, whichClass: CompClass, ftNet: Net _ NIL, equivPortClass: Rope.ROPE _ NIL, compClassSel: SELECT OVERLAID CompClass FROM ft, logic => [ preRow, curRow, initRow, fnlRow: ZMaxRowSr _ 0], io => [ preSide, curSide, initSide, fnlSide: SC.SideOrNone _ none], ENDCASE]; OrientationOrNone: TYPE = NAT[0 .. maxOrien]; Orientation: TYPE = OrientationOrNone[1 .. maxOrien]; maxOrien: NAT = 8; PinNets: TYPE = REF PinNetsRec; PinNetsRec: TYPE = RECORD[n: SEQUENCE size: NAT OF PinNet]; PinNet: TYPE = RECORD [ pin: ObjectPin _ NIL, net: Net _ NIL]; PinType: TYPE = {compPin, exitPin}; maxNets: NAT = 5000; MaxNetsSr: TYPE = NAT[1 .. maxNets]; ZMaxNetsSr: TYPE = NAT[0 .. maxNets]; Net: TYPE = REF NetRec; NetList: TYPE = LIST OF Net; Nets: TYPE = REF NetsRec; NetsRec: TYPE = RECORD [ count: ZMaxNetsSr _ 0, nets: NetArrayRef]; NetArray: TYPE = ARRAY MaxNetsSr OF Net _ ALL[NIL]; NetArrayRef: TYPE = REF NetArray; NetRec: TYPE = RECORD [ name: Rope.ROPE _ NIL, netNum: MaxNetsSr, trunkWidth, branchWidth: SC.Number _ 0, pins: NetPinsList _ NIL, feedThrusAllowed: BOOLEAN _ TRUE, acBus: AcBus _ NIL, externNet: ExtNet _ internalNet, ftsOnRow: RowSet, rowExits: ARRAY LRSide OF ChanSet, bounds1, bounds2: WireSeg _ NIL, minPinDist: SC.Number _ 0, lastEntry: WireSegPin _ NIL, pinsOnChan: NAT _ 0, chanConnect: ChanConnect _ ALL[]]; ExtNet: TYPE = {externalNet, internalNet}; NetPinsList: TYPE = LIST OF NetPin; NetPin: TYPE = REF NetPinRec; NetPinRec: TYPE = RECORD [ pinClass: PinType, instance: Instance _ NIL, pin: ObjectPin _ NIL, side: SC.SideOrNone _ none, chan: ZMaxChanSr _ 0 ]; maxPos: NAT = 1000; MaxPosSr: TYPE = NAT[1 .. maxPos]; ZMaxPosSr: TYPE = NAT[0 .. maxPos]; BpRow: TYPE = REF BpRowRec; BpRows: TYPE = REF BpRowsRec; BpRowsRec: TYPE = ARRAY SC.Side OF BpRow _ ALL[NIL]; BpRowRec: TYPE = RECORD [ bpSpacing: INT _ 0, size, sideOrg: RTBasic.PQPos _ [0, 0], dimInvalid: BOOLEAN _ TRUE, initMaxBpsOnSide, maxBpsOnSide, nBpsOnSide: ZMaxPosSr _ 0, bpsOnSide: ARRAY ZMaxPosSr OF Instance _ ALL[NIL], fnlBpFxd, initBpFxd, routeSideChans: BOOLEAN _ FALSE]; maxLgRows: NAT = 50; MaxRowSr: TYPE = NAT[1 .. maxLgRows]; ZMaxRowSr: TYPE = NAT[0 .. maxLgRows]; LgRow: TYPE = REF LgRowRec; LgRows: TYPE = REF LgRowsRec; LgRowsRec: TYPE = RECORD [ horzRowOrg, maxRowWidth: SC.Number _ 0, numMaxRows: NAT _ 0, count: ZMaxRowSr _ 0, rows: ARRAY MaxRowSr OF LgRow _ ALL[NIL]]; LgRowRec: TYPE = RECORD [ size, rowOrg: RTBasic.PQPos _ [0, 0], dimInvalid: BOOLEAN _ TRUE, rowNum: NAT, nLgsOnRow, nFtsOnRow: ZMaxPosSr _ 0, lgsOnRow: ARRAY MaxPosSr OF Instance _ ALL[NIL], fnlLgFxd, initLgFxd: BOOLEAN _ FALSE]; maxChans: NAT = maxLgRows + 1; MaxChanSr: TYPE = NAT[1 .. maxChans]; ZMaxChanSr: TYPE = NAT[0 .. maxChans]; RowChan: TYPE = REF RowChanRec; RowChans: TYPE = REF RowChansRec; RowChansRec: TYPE = RECORD [ count: ZMaxChanSr _ 0, totNetChans: NAT, chans: ARRAY MaxChanSr OF RowChan _ ALL[NIL]]; RowChanRec: TYPE = RECORD [ routeType: RouteType _ maxRoute, chanNum: NAT, initChanWidth, chanWidth, minChanWidth, chanResult, chanPos, wireLength: SC.Number _ 0, numTracks: NAT _ 0, numExits: ARRAY LRSide OF ZMaxExitsSr _ [0, 0], exits: ExitArray, netChans: NAT]; ExitArrayOb: TYPE = ARRAY LRSide OF ARRAY MaxExitsSr OF Exit; ExitArray: TYPE = REF ExitArrayOb; maxExits: NAT = 1000; MaxExitsSr: TYPE = NAT[1 .. maxExits]; ZMaxExitsSr: TYPE = NAT[0 .. maxExits]; Exit: TYPE = RECORD [ net: Net _ NIL, pos: SC.Number _ 0, -- track number layer: SC.Layer]; SideChan: TYPE = REF SideChanRec; SideChans: TYPE = ARRAY LRSide OF SideChan; SideChanRec: TYPE = RECORD [ side: SC.Side, initSideChanWidth, sideChanWidth, minSideChanWidth, sideChanResult, sideChanPos, wireLength: SC.Number _ 0, sideChanTracks: NAT _ 0]; PowerBuses: TYPE = ARRAY LRSide OF PowerBus; PowerBus: TYPE = REF PowerBusRec; PowerBusRec: TYPE = RECORD [ name: Rope.ROPE, net: Net _ NIL, onSide: LRSide, fromTB: TBSide _ top, width: SC.Number _ 0]; AcBuses: TYPE = ARRAY LRSide OF AcBusSides; AcBusSides: TYPE = REF AcBusSidesRec; AcBusSidesRec: TYPE = RECORD [ count: ZMAcBusSr _ 0, width: SC.Number _ 0, sigs: AcBusSigs _ NIL]; AcBus: TYPE = REF AcBusRec; AcBusSigs: TYPE = REF AcBusSigsRec; AcBusSigsRec: TYPE = RECORD [ c: SEQUENCE size: NAT OF AcBus]; maxClocks: NAT = 20; MAcBusSr: TYPE = NAT[1 .. maxObjects]; -- clock definitions ZMAcBusSr: TYPE = NAT[0 .. maxObjects]; -- clock definitions AcBusRec: TYPE = RECORD [ name: Rope.ROPE, net: Net _ NIL, onSide: LRSide, fromTB: TBSide_ top, depth: SC.Number _ 0]; maxWireSegs: NAT = 2000; MaxWireSegsSr: TYPE = NAT[1 .. maxWireSegs]; ZMaxWireSegsSr: TYPE = NAT[0 .. maxWireSegs]; WireSegs: TYPE = REF WireSegsRec; WireSegsRec: TYPE = RECORD [ nWireSegsOnCh: ZMaxWireSegsSr _ 0, segs: ARRAY SCPrivate.MaxWireSegsSr OF WireSeg _ ALL[NIL]]; WireSeg: TYPE = REF WireSegRec; WireSegRec: TYPE = RECORD [ pos: SC.Number, endType: SC.Side]; maxPinsOnCh: NAT = 2000; MaxPinsOnChSr: TYPE = NAT[1 .. maxPinsOnCh]; ZMaxPinsOnChSr: TYPE = NAT[0 .. maxPinsOnCh]; WireSegPins: TYPE = REF WireSegPinsRec; WireSegPinsRec: TYPE = RECORD [ nPinsOnCh: ZMaxWireSegsSr _ 0, pins: ARRAY SCPrivate.MaxPinsOnChSr OF WireSegPin _ ALL[NIL]]; PinArrayOb: TYPE = ARRAY SCPrivate.MaxPinsOnChSr OF WireSegPin _ ALL[NIL]; PinArray: TYPE = REF PinArrayOb; WireSegPin: TYPE = REF WireSegPinRec; WireSegPinRec: TYPE = RECORD [ pos: SC.Number, net: SCPrivate.Net, side: SC.Side]; RouteType: TYPE = {minRoute, maxRoute}; FomType: TYPE = {areaFom, wlFom}; GetStructure: PROC [handle: SC.Handle, cellType: Core.CellType] RETURNS [done: BOOLEAN]; SetUpLayout: PROC [handle: SC.Handle] RETURNS [done: BOOLEAN]; DetailRoute: PROC [handle: SC.Handle] RETURNS [result: SC.Result]; PosImprove: PROC [handle: SC.Handle, whichFom: FomType]; SAPlace: PROC [handle: SC.Handle, t0, alpha: REAL, seed: INT]; END. jSCPrivate.mesa ///StdCell/SCPrivate.mesa Copyright c 1985 by Xerox Corporation. All rights reserved. by Bryan Preas, July 10, 1985 11:48:30 am PDT last edited by Bryan Preas, July 17, 1985 12:26:15 pm PDT Frank Bowers February 6, 1986 8:00:02 am PST bonding pad and logic component types ftNet: Net _ NIL], equivPortClass: Rope.ROPE _ NIL], interconnection net types should be a variant record np: SELECT pinClass: PinType FROM compPin => [ instance: Instance _ NIL, pin: ObjectPin _ NIL}, exitPin => [ side: SC.SideOrNone _ none, chan: ZMaxChanSr _ 0}; ENDCASE bonding pad side and logic row types Κ|˜šœ*™*Jšœ Οmœ1™—Jš œ žœžœžœžœžœ˜JJšœ žœžœ ˜ Jšœ žœžœ˜%šœžœžœ˜Jšœžœ˜Jšœ˜Jšœžœ˜—J˜Jšœ žœ˜'Jšœ žœ˜!J˜šΟn œžœ žœ!˜?Kšžœžœ˜—J˜š  œžœ žœ˜%Kšžœžœ˜K˜—Jš   œžœ žœ žœ žœ ˜BJ˜Jš  œžœ žœ˜8J˜Jš  œžœ žœžœžœ˜>Jšžœ˜—J˜J˜J˜—…—#4ό