DIRECTORY CD, CDSimpleRules, Core, CoreCompose, Rope, Route, RTBasic, SC, SCChanUtil, SCInitialPlace, SCInstUtil, SCPlaceUtil, SCPrivate, SCRowUtil, SCSmash, SCWidthUtil, SCUtil; SCImpl: CEDAR PROGRAM IMPORTS CD, CDSimpleRules, Route, RTBasic, SC, SCChanUtil, SCInitialPlace, SCInstUtil, SCPlaceUtil, SCPrivate, SCRowUtil, SCSmash, SCWidthUtil, SCUtil EXPORTS SC SHARES SC = { debug: BOOLEAN _ FALSE; Error: PUBLIC ERROR[errorType: SC.ErrorType _ callingError, explanation: Rope.ROPE _ NIL] = CODE; Signal: PUBLIC SIGNAL[signalType: SC.ErrorType _ callingError, explanation: Rope.ROPE _ NIL] = CODE; CreateDesignRules: PUBLIC PROC [technologyKey: ATOM, horizLayer, vertLayer: Rope.ROPE, rowDirection: SC.Direction, properties: SC.PropList _ NIL] RETURNS [designRules: SC.DesignRules] = BEGIN hLayer, vLayer: SC.Layer; designRules _ NEW[SC.DesignRulesRec]; designRules.technology _ CD.FetchTechnology[technologyKey]; hLayer _ CDSimpleRules.GetLayer[technologyKey, horizLayer]; vLayer _ CDSimpleRules.GetLayer[technologyKey, vertLayer]; designRules.horizLayer _ horizLayer; designRules.vertLayer _ vertLayer; designRules.rowRules _ Route.CreateDesignRules[technologyKey, hLayer, vLayer, rowDirection, properties]; designRules.sideRules _ Route.CreateDesignRules[technologyKey, hLayer, vLayer, RTBasic.OtherDirection[rowDirection], properties]; END; CreateHandle: PUBLIC PROC [coreContext: CoreCompose.Context, cellType: Core.CellType, cdDesign, libDesign: CD.Design, designRules: SC.DesignRules, name: Rope.ROPE, properties: SC.PropList _ NIL] RETURNS [handle: SC.Handle] = BEGIN parms: SCPrivate.Parms _ NARROW[NEW[SCPrivate.ParmsRec], SCPrivate.Parms]; IF designRules = NIL THEN SC.Signal[callingError, "No design rules."]; IF coreContext = NIL THEN SC.Signal[callingError, "No Core context."]; IF libDesign = NIL THEN SC.Signal[callingError, "No ChipNDale library."]; handle _ NEW[SC.HandleRec]; handle.name _ name; handle.rules _ designRules; handle.properties _ properties; handle.coreContext _ coreContext; parms.libDesign _ libDesign; parms.cdDesign _ cdDesign; handle.parms _ parms; IF ~SCPrivate.SetUpLayout[handle] THEN SC.Signal[callingError, "Unable to construct layout data"]; IF ~SCPrivate.GetStructure[handle, cellType] THEN SC.Signal[callingError, "Unable to construct structure data"]; END; InitialPlace: PUBLIC PROC [handle: SC.Handle, numRows: NAT _ 0] = { layoutData: SCPrivate.LayoutData _ NARROW[handle.layoutData]; SCSmash.RemoveSmash[handle]; SCPlaceUtil.ClrCurPlac[handle, TRUE]; SCChanUtil.InitChanWidths[handle]; SCInitialPlace.PrePlace[handle, numRows, TRUE]; SCInitialPlace.RowInit[handle]; SCInitialPlace.PosInit[handle]; [layoutData.lgRows.maxRowWidth, layoutData.lgRows.numMaxRows] _ SCRowUtil.FindMaxRow[handle]; SCWidthUtil.AllChanWidths[handle, areaFom]; SCInstUtil.AsgnChanPos[handle]; IF debug THEN SCPlaceUtil.WriteCurPlace[handle]; [] _ SCUtil.WriteResults["End initial placement\n initial size: ", handle, 0]}; PlaceImprove: PUBLIC PROC [handle: SC.Handle, algorithm: ATOM] = { SELECT algorithm FROM $simulatedAnealing =>NULL; $pairWiseImprovement =>NULL; $globalRouting => SCPrivate.PosImprove[handle, areaFom]; ENDCASE}; GlobalRoute: PUBLIC PROC [handle: SC.Handle] = { SCSmash.RemoveSmash[handle]; SCSmash.SmashAllNets[handle, TRUE]}; DetailRoute: PUBLIC PROC [handle: SC.Handle] RETURNS [result: SC.Result] = { result _ SCPrivate.DetailRoute[handle]}; CreateLayout: PUBLIC PROC [technologyKey: ATOM, horizLayer, vertLayer: Rope.ROPE, rowDirection: SC.Direction, numRows: NAT, coreContext: CoreCompose.Context, cellType: Core.CellType, cdDesign, libDesign: CD.Design _ NIL, name: Rope.ROPE _ NIL, properties: SC.PropList _ NIL] RETURNS [object: CD.Object] = { result: SC.Result; designRules: SC.DesignRules _ SC.CreateDesignRules[technologyKey, horizLayer, vertLayer, rowDirection, properties]; handle: SC.Handle _ SC.CreateHandle[coreContext, cellType, cdDesign, libDesign, designRules, name, properties]; SC.InitialPlace[handle, 0]; SC.PlaceImprove[handle, $pairWiseImprovement]; SC.GlobalRoute[handle]; result _ SC.DetailRoute[handle]; RETURN [result.object]; }; }. \SCImpl.mesa ///StdCell/SCImpl.mesa Copyright c 1985 by Xerox Corporation. All rights reserved. Bryan Preas, November 7, 1985 10:11:54 am PST Define the standard cell design rules. technologyKey values are predefinded for now. horizLayer, vertLayer should be "poly", "metal" or "metal2". Create a standard cell design. The standard cell design definition includes the design rules (conductor and via widths and spacings) and the circuit definition. set up the layout data set up the structure data Determine an initial placement for the instances. Improve the placement for the instances. Available algorithms consist of the following: $simulatedAnealing, $pairWiseImprovement Determine strategic paths for the wiring that must cross cell rows. Determine actual wiring paths. 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