SCPrivate.mesa ///StdCell/SCPrivate.mesa
Copyright © 1985 by Xerox Corporation. All rights reserved.
by Bryan Preas, July 10, 1985 11:48:30 am PDT
last edited by Bryan Preas, July 17, 1985 12:26:15 pm PDT
Frank Bowers February 6, 1986 8:00:02 am PST
DIRECTORY
CD,
Core,
D2Basic,
Rope,
Route,
RTSets,
RTBasic,
SC;
SCPrivate: CEDAR DEFINITIONS =
BEGIN
CompClass: TYPE = {other, logic, io, ft}; 
DegreeOfConnection: TYPE = {full, min, none};
ChanConnect: TYPE = PACKED ARRAY RTSets.RTMdSetRange OF DegreeOfConnection ← ALL[none];
LRSide: TYPE = RTBasic.LRSide;
TBSide: TYPE = RTBasic.TBSide;
LRSideSet: TYPE = RTSets.RTSmSet -- OF Lrsidetype -- ;
SideSet: TYPE = RTSets.RTSmSet -- OF Validside -- ;
RowSet: TYPE = RTSets.RTMdSet -- OF Maxrowsr -- ;
ChanSet: TYPE = RTSets.RTMdSet -- OF Maxchansr -- ;
StructureData: TYPE = REF StructureDataRec;
StructureDataRec: TYPE = RECORD [
objects: Objects ← NIL,
instances: Instances ← NIL,
nets: Nets ← NIL];
LayoutData: TYPE = REF LayoutDataRec;
LayoutDataRec: TYPE = RECORD [
totWidth, totHeight: SC.Number ← 0,
bpRows: BpRows ← NIL,
lgRows: LgRows ← NIL,
sideChans: SideChans ← [NIL, NIL],
rowChans: RowChans ← NIL,
acBuses: AcBuses ← [NIL, NIL],
powerBuses: PowerBuses ← [NIL, NIL],
layoutParms: LayoutParms,
wireSegs: WireSegs ← NIL,
wireSegPins: WireSegPins ← NIL,
globalRoute: REF ANYNIL];
Parms: TYPE = REF ParmsRec;
ParmsRec: TYPE = RECORD [
cdDesign, libDesign: CD.Design ← NIL,
ftObject, portObject: Object ← NIL];
LayoutParms: TYPE = REF LayoutParmsRec;
LayoutParmsRec: TYPE = RECORD [
whichFom: FomType ← wlFom,
useMaxRouteExits, useInteriorChanExits: BOOLEANTRUE,
numRows: NAT ← 0,
rowDirection: SC.Direction ← horizontal,
unitsPerLam: SC.Number ← 2,
powerName: ARRAY LRSide OF Rope.ROPE];
maxObjects: NAT = 100;
maxPinsOnObject: NAT = 100;
MaxObjectsSr: TYPE = NAT[1 .. maxObjects]; -- Object definitions
ZMaxObjectsSr: TYPE = NAT[0 .. maxObjects]; -- Object definitions
Objects: TYPE = REF ObjectsRec;
ObjectsRec: TYPE = RECORD [
count: ZMaxObjectsSr ← 0,
ob: ARRAY MaxObjectsSr OF Object ← ALL[NIL]];
Object: TYPE = REF ObjectRec;
ObjectRec: TYPE = RECORD [
name: Rope.ROPENIL,
objectNum: MaxObjectsSr,
size, orgin: RTBasic.PQPos ← [0, 0],
numPins: NAT ← 0,
pins: ObjectPins ← NIL,
typeClass: CompClass ← other,
numTimesUsed: NAT ← 0,
cdOb: CD.Object ← NIL];
ObjectPin: TYPE = REF ObjectPinRec;
ObjectPins: TYPE = REF ObjectPinsRec;
ObjectPinsRec: TYPE = RECORD [
p: SEQUENCE size: NAT OF ObjectPin];
ObjectPinRec: TYPE = RECORD [
name: Rope.ROPENIL,
pinPos: PinPos,
cdPin: CD.Instance ← NIL,
rect: SC.Rect ← [0, 0, 0, 0],
layer: SC.Layer,
equivClass: Rope.ROPENIL];
PinPos: TYPE = RECORD [
side: SC.SideOrNone ← none,
depth, location: SC.Number ← 0];
bonding pad and logic component types
maxInstance: NAT = 5000;
MaxInstanceSr: TYPE = NAT[1 .. maxInstance];
ZMaxInstanceSr: TYPE = NAT[0 .. maxInstance];
Instance: TYPE = REF InstanceRec;
InstanceList: TYPE = LIST OF Instance;
Instances: TYPE = REF InstancesRec;
InstancesRec: TYPE = RECORD [
count, numIOs, numLogics, numFts: ZMaxInstanceSr ← 0,
inst: Insts ← NIL];
Insts: TYPE = REF InstsOb;
InstsOb: TYPE = ARRAY MaxInstanceSr OF Instance ← ALL[NIL];
InstanceRec: TYPE = RECORD [
name: Rope.ROPE,
instanceNum: MaxInstanceSr,
object: Object ← NIL,
pinNets: PinNets ← NIL,
prePos, curPos, initPos, fnlPos: ZMaxPosSr ← 0,
preOrien, curOrien, initOrien, fnlOrien: OrientationOrNone ← 0,
offset: SC.Number ← 0,
whichClass: CompClass,
ftNet: Net ← NIL,
equivPortClass: Rope.ROPENIL,
compClassSel: SELECT OVERLAID CompClass FROM
ft, logic => [
preRow, curRow, initRow, fnlRow: ZMaxRowSr ← 0],
ftNet: Net ← NIL],
io => [
preSide, curSide, initSide, fnlSide: SC.SideOrNone ← none],
equivPortClass: Rope.ROPE ← NIL],
ENDCASE];
OrientationOrNone: TYPE = NAT[0 .. maxOrien];
Orientation: TYPE = OrientationOrNone[1 .. maxOrien];
maxOrien: NAT = 8;
PinNets: TYPE = REF PinNetsRec;
PinNetsRec: TYPE = RECORD[n: SEQUENCE size: NAT OF PinNet];
PinNet: TYPE = RECORD [
pin: ObjectPin ← NIL,
net: Net ← NIL];
interconnection net types
PinType: TYPE = {compPin, exitPin};
maxNets: NAT = 5000;
MaxNetsSr: TYPE = NAT[1 .. maxNets];
ZMaxNetsSr: TYPE = NAT[0 .. maxNets];
Net: TYPE = REF NetRec;
NetList: TYPE = LIST OF Net;
Nets: TYPE = REF NetsRec;
NetsRec: TYPE = RECORD [
count: ZMaxNetsSr ← 0,
nets: NetArrayRef];
NetArray: TYPE = ARRAY MaxNetsSr OF Net ← ALL[NIL];
NetArrayRef: TYPE = REF NetArray;
NetRec: TYPE = RECORD [
name: Rope.ROPENIL,
netNum: MaxNetsSr,
trunkWidth, branchWidth: SC.Number ← 0,
pins: NetPinsList ← NIL,
feedThrusAllowed: BOOLEANTRUE,
acBus: AcBus ← NIL,
externNet: ExtNet ← internalNet,
ftsOnRow: RowSet,
rowExits: ARRAY LRSide OF ChanSet,
bounds1, bounds2: WireSeg ← NIL,
minPinDist: SC.Number ← 0,
lastEntry: WireSegPin ← NIL,
pinsOnChan: NAT ← 0,
chanConnect: ChanConnect ← ALL[]];
ExtNet: TYPE = {externalNet, internalNet};
NetPinsList: TYPE = LIST OF NetPin;
NetPin: TYPE = REF NetPinRec;
NetPinRec: TYPE = RECORD [
pinClass: PinType,
instance: Instance ← NIL,
pin: ObjectPin ← NIL,
side: SC.SideOrNone ← none,
chan: ZMaxChanSr ← 0
should be a variant record
np: SELECT pinClass: PinType FROM
compPin => [
instance: Instance ← NIL,
pin: ObjectPin ← NIL},
exitPin => [
side: SC.SideOrNone ← none,
chan: ZMaxChanSr ← 0};
ENDCASE
];
maxPos: NAT = 1000;
MaxPosSr: TYPE = NAT[1 .. maxPos];
ZMaxPosSr: TYPE = NAT[0 .. maxPos];
bonding pad side and logic row types
BpRow: TYPE = REF BpRowRec;
BpRows: TYPE = REF BpRowsRec;
BpRowsRec: TYPE = ARRAY SC.Side OF BpRow ← ALL[NIL];
BpRowRec: TYPE = RECORD [
bpSpacing: INT ← 0,
size, sideOrg: RTBasic.PQPos ← [0, 0],
dimInvalid: BOOLEANTRUE,
initMaxBpsOnSide, maxBpsOnSide, nBpsOnSide: ZMaxPosSr ← 0,
bpsOnSide: ARRAY ZMaxPosSr OF Instance ← ALL[NIL],
fnlBpFxd, initBpFxd, routeSideChans: BOOLEANFALSE];
maxLgRows: NAT = 50;
MaxRowSr: TYPE = NAT[1 .. maxLgRows];
ZMaxRowSr: TYPE = NAT[0 .. maxLgRows];
LgRow: TYPE = REF LgRowRec;
LgRows: TYPE = REF LgRowsRec;
LgRowsRec: TYPE = RECORD [
horzRowOrg, maxRowWidth: SC.Number ← 0,
numMaxRows: NAT ← 0,
count: ZMaxRowSr ← 0,
rows: ARRAY MaxRowSr OF LgRow ← ALL[NIL]];
LgRowRec: TYPE = RECORD [
size, rowOrg: RTBasic.PQPos ← [0, 0],
dimInvalid: BOOLEANTRUE,
rowNum: NAT,
nLgsOnRow, nFtsOnRow: ZMaxPosSr ← 0,
lgsOnRow: ARRAY MaxPosSr OF Instance ← ALL[NIL],
fnlLgFxd, initLgFxd: BOOLEANFALSE];
maxChans: NAT = maxLgRows + 1;
MaxChanSr: TYPE = NAT[1 .. maxChans];
ZMaxChanSr: TYPE = NAT[0 .. maxChans];
RowChan: TYPE = REF RowChanRec;
RowChans: TYPE = REF RowChansRec;
RowChansRec: TYPE = RECORD [
count: ZMaxChanSr ← 0,
totNetChans: NAT,
chans: ARRAY MaxChanSr OF RowChan ← ALL[NIL]];
RowChanRec: TYPE = RECORD [
routeType: RouteType ← maxRoute,
chanNum: NAT,
initChanWidth, chanWidth, minChanWidth, chanResult, chanPos, wireLength: SC.Number ← 0,
numTracks: NAT ← 0,
numExits: ARRAY LRSide OF ZMaxExitsSr ← [0, 0],
exits: ExitArray,
netChans: NAT];
ExitArrayOb: TYPE = ARRAY LRSide OF ARRAY MaxExitsSr OF Exit;
ExitArray: TYPE = REF ExitArrayOb;
maxExits: NAT = 1000;
MaxExitsSr: TYPE = NAT[1 .. maxExits];
ZMaxExitsSr: TYPE = NAT[0 .. maxExits];
Exit: TYPE = RECORD [
net: Net ← NIL,
pos: SC.Number ← 0, -- track number
layer: SC.Layer];
SideChan: TYPE = REF SideChanRec;
SideChans: TYPE = ARRAY LRSide OF SideChan;
SideChanRec: TYPE = RECORD [
side: SC.Side,
initSideChanWidth, sideChanWidth, minSideChanWidth, sideChanResult, sideChanPos, wireLength: SC.Number ← 0,
sideChanTracks: NAT ← 0];
PowerBuses: TYPE = ARRAY LRSide OF PowerBus;
PowerBus: TYPE = REF PowerBusRec;
PowerBusRec: TYPE = RECORD [
name: Rope.ROPE,
net: Net ← NIL,
onSide: LRSide,
fromTB: TBSide ← top,
width: SC.Number ← 0];
AcBuses: TYPE = ARRAY LRSide OF AcBusSides;
AcBusSides: TYPE = REF AcBusSidesRec;
AcBusSidesRec: TYPE = RECORD [
count: ZMAcBusSr ← 0,
width: SC.Number ← 0,
sigs: AcBusSigs ← NIL];
AcBus: TYPE = REF AcBusRec;
AcBusSigs: TYPE = REF AcBusSigsRec;
AcBusSigsRec: TYPE = RECORD [
c: SEQUENCE size: NAT OF AcBus];
maxClocks: NAT = 20;
MAcBusSr: TYPE = NAT[1 .. maxObjects]; -- clock definitions
ZMAcBusSr: TYPE = NAT[0 .. maxObjects]; -- clock definitions
AcBusRec: TYPE = RECORD [
name: Rope.ROPE,
net: Net ← NIL,
onSide: LRSide,
fromTB: TBSide← top,
depth: SC.Number ← 0];
maxWireSegs: NAT = 2000;
MaxWireSegsSr: TYPE = NAT[1 .. maxWireSegs];
ZMaxWireSegsSr: TYPE = NAT[0 .. maxWireSegs];
WireSegs: TYPE = REF WireSegsRec;
WireSegsRec: TYPE = RECORD [
nWireSegsOnCh: ZMaxWireSegsSr ← 0,
segs: ARRAY SCPrivate.MaxWireSegsSr OF WireSeg ← ALL[NIL]];
WireSeg: TYPE = REF WireSegRec;
WireSegRec: TYPE = RECORD [
pos: SC.Number,
endType: SC.Side];
maxPinsOnCh: NAT = 2000;
MaxPinsOnChSr: TYPE = NAT[1 .. maxPinsOnCh];
ZMaxPinsOnChSr: TYPE = NAT[0 .. maxPinsOnCh];
WireSegPins: TYPE = REF WireSegPinsRec;
WireSegPinsRec: TYPE = RECORD [
nPinsOnCh: ZMaxWireSegsSr ← 0,
pins: ARRAY SCPrivate.MaxPinsOnChSr OF WireSegPin ← ALL[NIL]];
PinArrayOb: TYPE = ARRAY SCPrivate.MaxPinsOnChSr OF WireSegPin ← ALL[NIL];
PinArray: TYPE = REF PinArrayOb;
WireSegPin: TYPE = REF WireSegPinRec;
WireSegPinRec: TYPE = RECORD [
pos: SC.Number,
net: SCPrivate.Net,
side: SC.Side];
RouteType: TYPE = {minRoute, maxRoute};
FomType: TYPE = {areaFom, wlFom};
GetStructure: PROC [handle: SC.Handle, cellType: Core.CellType]
RETURNS [done: BOOLEAN];
SetUpLayout: PROC [handle: SC.Handle]
RETURNS [done: BOOLEAN];
DetailRoute: PROC [handle: SC.Handle] RETURNS [result: SC.Result];
PosImprove: PROC [handle: SC.Handle, whichFom: FomType];
SAPlace: PROC [handle: SC.Handle, t0, alpha: REAL, seed: INT];
END.