SCImpl.mesa ///StdCell/SCImpl.mesa
Copyright © 1985 by Xerox Corporation. All rights reserved.
Bryan Preas, November 7, 1985 10:11:54 am PST
DIRECTORY
CD,
CDSimpleRules,
Core,
CoreCompose,
Rope,
Route,
RTBasic,
SC,
SCChanUtil,
SCInitialPlace,
SCInstUtil,
SCPlaceUtil,
SCPrivate,
SCRowUtil,
SCSmash,
SCWidthUtil,
SCUtil;
SCImpl: CEDAR PROGRAM
IMPORTS CD, CDSimpleRules, Route, RTBasic, SC, SCChanUtil, SCInitialPlace, SCInstUtil, SCPlaceUtil, SCPrivate, SCRowUtil, SCSmash, SCWidthUtil, SCUtil
EXPORTS SC
SHARES SC = {
debug: BOOLEANFALSE;
Error: PUBLIC ERROR[errorType: SC.ErrorType ← callingError, explanation: Rope.ROPENIL] = CODE;
Signal: PUBLIC SIGNAL[signalType: SC.ErrorType ← callingError, explanation: Rope.ROPENIL] = CODE;
CreateDesignRules: PUBLIC PROC [technologyKey: ATOM, horizLayer, vertLayer: Rope.ROPE, rowDirection: SC.Direction, properties: SC.PropList ← NIL] RETURNS [designRules: SC.DesignRules] =
Define the standard cell design rules. technologyKey values are predefinded for now. horizLayer, vertLayer should be "poly", "metal" or "metal2".
BEGIN
hLayer, vLayer: SC.Layer;
designRules ← NEW[SC.DesignRulesRec];
designRules.technology ← CD.FetchTechnology[technologyKey];
hLayer ← CDSimpleRules.GetLayer[technologyKey, horizLayer];
vLayer ← CDSimpleRules.GetLayer[technologyKey, vertLayer];
designRules.horizLayer ← horizLayer;
designRules.vertLayer ← vertLayer;
designRules.rowRules ← Route.CreateDesignRules[technologyKey, hLayer, vLayer, rowDirection, properties];
designRules.sideRules ← Route.CreateDesignRules[technologyKey, hLayer, vLayer, RTBasic.OtherDirection[rowDirection], properties];
END;
CreateHandle: PUBLIC PROC [coreContext: CoreCompose.Context, cellType: Core.CellType, cdDesign, libDesign: CD.Design, designRules: SC.DesignRules, name: Rope.ROPE, properties: SC.PropList ← NIL] RETURNS [handle: SC.Handle] =
Create a standard cell design. The standard cell design definition includes the design rules (conductor and via widths and spacings) and the circuit definition.
BEGIN
parms: SCPrivate.Parms ← NARROW[NEW[SCPrivate.ParmsRec], SCPrivate.Parms];
IF designRules = NIL THEN SC.Signal[callingError, "No design rules."];
IF coreContext = NIL THEN SC.Signal[callingError, "No Core context."];
IF libDesign = NIL THEN SC.Signal[callingError, "No ChipNDale library."];
handle ← NEW[SC.HandleRec];
handle.name ← name;
handle.rules ← designRules;
handle.properties ← properties;
handle.coreContext ← coreContext;
parms.libDesignlibDesign;
parms.cdDesign ← cdDesign;
handle.parms ← parms;
set up the layout data
IF ~SCPrivate.SetUpLayout[handle] THEN
SC.Signal[callingError, "Unable to construct layout data"];
set up the structure data
IF ~SCPrivate.GetStructure[handle, cellType] THEN
SC.Signal[callingError, "Unable to construct structure data"];
END;
InitialPlace: PUBLIC PROC [handle: SC.Handle, numRows: NAT ← 0] = {
Determine an initial placement for the instances.
layoutData: SCPrivate.LayoutData ← NARROW[handle.layoutData];
SCSmash.RemoveSmash[handle];
SCPlaceUtil.ClrCurPlac[handle, TRUE];
SCChanUtil.InitChanWidths[handle];
SCInitialPlace.PrePlace[handle, numRows, TRUE];
SCInitialPlace.RowInit[handle];
SCInitialPlace.PosInit[handle];
[layoutData.lgRows.maxRowWidth, layoutData.lgRows.numMaxRows] ← SCRowUtil.FindMaxRow[handle];
SCWidthUtil.AllChanWidths[handle, areaFom];
SCInstUtil.AsgnChanPos[handle];
IF debug THEN SCPlaceUtil.WriteCurPlace[handle];
[] ← SCUtil.WriteResults["End initial placement\n initial size: ", handle, 0]};
PlaceImprove: PUBLIC PROC [handle: SC.Handle, algorithm: ATOM] = {
Improve the placement for the instances. Available algorithms consist of the following: $simulatedAnealing, $pairWiseImprovement
SELECT algorithm FROM
$simulatedAnealing =>NULL;
$pairWiseImprovement =>NULL;
$globalRouting => SCPrivate.PosImprove[handle, areaFom];
ENDCASE};
GlobalRoute: PUBLIC PROC [handle: SC.Handle] = {
Determine strategic paths for the wiring that must cross cell rows.
SCSmash.RemoveSmash[handle];
SCSmash.SmashAllNets[handle, TRUE]};
DetailRoute: PUBLIC PROC [handle: SC.Handle] RETURNS [result: SC.Result] = {
Determine actual wiring paths.
result ← SCPrivate.DetailRoute[handle]};
CreateLayout: PUBLIC PROC [technologyKey: ATOM, horizLayer, vertLayer: Rope.ROPE, rowDirection: SC.Direction, numRows: NAT, coreContext: CoreCompose.Context, cellType: Core.CellType, cdDesign, libDesign: CD.Design ← NIL, name: Rope.ROPENIL, properties: SC.PropList ← NIL] RETURNS [object: CD.Object] = {
Create a standard cell object by performing the above operations
result: SC.Result;
designRules: SC.DesignRules ← SC.CreateDesignRules[technologyKey, horizLayer, vertLayer, rowDirection, properties];
handle: SC.Handle ← SC.CreateHandle[coreContext, cellType, cdDesign, libDesign, designRules, name, properties];
SC.InitialPlace[handle, 0];
SC.PlaceImprove[handle, $pairWiseImprovement];
SC.GlobalRoute[handle];
result ← SC.DetailRoute[handle];
RETURN [result.object];
};
}.