SCTestPW.mesa
Copyright © 1985 by Xerox Corporation. All rights reserved.
Last Edited by: Preas, September 5, 1985 10:39:21 am PDT
Bryan Preas September 5, 1985 10:37:21 am PDT
Use with the file SCTestPW.dale to test routing:
SC.load
cdread SCTestPW -- NOTE: SCTest.dale must be in the /// directory
run SCTestPW
middle click P in the ChipNDale viewer
select the appropriate generator
DIRECTORY
CD,
Core,
CoreCreate,
CoreOps,
CoreClasses,
IO,
PW,
Rope,
SC,
ViewerIO;
SCTestPW: CEDAR PROGRAM
IMPORTS CD, CoreCreate, CoreOps, PW, SC, ViewerIO
SHARES SC =
BEGIN
debug: BOOLEAN ← FALSE;
CreateCore: PROC [] RETURNS [Core.Design, Core.CellType] =
Create a Core design
BEGIN
andInst, invInst: CoreClasses.CellInstance;
coreDesign: Core.Design ← CoreOps.CreateDesign["SCTestPW"];
SCTestPW: Core.CellType ← CoreCreate.CreateRecordCell[coreDesign, "SCTestPW"];
nand: Core.CellType ← CoreCreate.CreateRecordCell[coreDesign, "NAND"];
inverter: Core.CellType ← CoreCreate.CreateRecordCell[coreDesign, "Inverter"];
[] ← CoreCreate.CreatePublicWire[coreDesign, SCTestPW, NIL, LIST["InA", "InB", "Out"]];
[] ← CoreCreate.CreatePublicWire[coreDesign, nand, NIL, LIST["InA", "InB", "Out"]];
[] ← CoreCreate.CreatePublicWire[coreDesign, inverter, NIL, LIST["In", "Out"]];
[] ← CoreCreate.CreateWire[coreDesign, SCTestPW, "NOut"];
andInst ← CoreCreate.CreateCellInstance[coreDesign, SCTestPW, nand, "InA: InA, InB: InB, Out: NOut", NIL, "andInst"];
invInst ← CoreCreate.CreateCellInstance[coreDesign, SCTestPW, inverter, "In: NOut, Out: Out", NIL, "invInst"];
RETURN [coreDesign, SCTestPW];
END;
DoLayout: PROC [coreDesign: Core.Design, cellType: Core.CellType, cdDesign, libDesign: CD.Design] RETURNS [result: SC.Result ← NIL] =
Create a standard cell object
BEGIN
technology: CD.Technology ← CD.FetchTechnology[$cmos];
metal: SC.Layer ← CD.FetchLayer[technology, $met];
metal2: SC.Layer ← CD.FetchLayer[technology, $met2];
rules: SC.DesignRules ← SC.CreateDesignRules[$cmos, metal, metal2, horizontal];
IF libDesign # NIL THEN
{handle: SC.Handle ← SC.CreateHandle[coreDesign, cellType, cdDesign, libDesign, rules];
SC.InitialPlace[handle];
SC.GlobalRoute[handle];
SC.PlaceImprove[handle, $globalRouting];
result ← SC.DetailRoute[handle]};
END;
WriteCore: PROC [coreDesign: Core.Design, debug: BOOLEAN] =
Write Core to a viewer
BEGIN
IF debug THEN {
out: IO.STREAM ← ViewerIO.CreateViewerStreams[
name: "Core: SCTestPW",
viewer: NIL,
editedStream: FALSE].out;
CoreOps.PrintDesign[coreDesign, out]};
END;
TestSCTiny: PW.UserProc =
BEGIN
coreDesign: Core.Design;
cellType: Core.CellType;
result: SC.Result;
libName: Rope.ROPE ←"SCTest.dale";
libDesign: CD.Design ← PW.OpenDesign[libName];
[coreDesign, cellType] ← CreateCore[];
WriteCore[coreDesign, debug];
result ← DoLayout[coreDesign, cellType, NIL, libDesign];
RETURN[result.object];
END;
PW.Register[TestSCTiny, "TestSCTiny"];
END.