///StdCell/SCTestA.mesa
Copyright © 1985 by Xerox Corporation. All rights reserved.
Last Edited by: Preas, September 5, 1985 10:39:21 am PDT
Bryan Preas September 5, 1985 10:37:21 am PDT
DIRECTORY
CD,
CDDirectory,
CDGenerate,
CDGenerateRemote,
CDIO,
CDOps,
Core,
CoreCreate,
CoreOps,
CoreClasses,
IO,
Rope,
SC,
TerminalIO,
ViewerIO;
SCTestA: CEDAR PROGRAM
IMPORTS CD, CDDirectory, CDGenerateRemote, CDIO, CDOps, CoreCreate, CoreOps, Rope, SC, TerminalIO, ViewerIO
SHARES SC =
BEGIN
CreateCore: PROC [] RETURNS [Core.Design, Core.CellType] =
Create a Core design
BEGIN
coreDesign: Core.Design ← CoreOps.CreateDesign["SCTestA"];
SCTestA: Core.CellType ← CoreCreate.CreateRecordCell[coreDesign, "SCTestA"];
nand: Core.CellType ← CoreCreate.CreateRecordCell[coreDesign, "NAND"];
cols: Core.Wire ← CoreCreate.CreatePublicWire[coreDesign, SCTestA, NIL, LIST["Col1", "Col2", "Col3", "Col4", "Col5"]];
rows: Core.Wire ← CoreCreate.CreatePublicWire[coreDesign, SCTestA, NIL, LIST["Row1", "Row2", "Row3", "Row4", "Row5"]];
outs: Core.Wire ← CoreCreate.CreatePublicWire[coreDesign, SCTestA, NIL, LIST["nandInst15W", "nandInst25W", "nandInst35W", "nandInst45W", "nandInst55W"]];
nandPorts: Core.Wire ← CoreCreate.CreatePublicWire[coreDesign, nand, NIL, LIST["InA", "InB", "Out"]];
nandInst11W: Core.Wire ← CoreCreate.CreateWire[coreDesign, SCTestA, "nandInst11W"];
nandInst12W: Core.Wire ← CoreCreate.CreateWire[coreDesign, SCTestA, "nandInst12W"];
nandInst13W: Core.Wire ← CoreCreate.CreateWire[coreDesign, SCTestA, "nandInst13W"];
nandInst14W: Core.Wire ← CoreCreate.CreateWire[coreDesign, SCTestA, "nandInst14W"];
nandInst21W: Core.Wire ← CoreCreate.CreateWire[coreDesign, SCTestA, "nandInst21W"];
nandInst22W: Core.Wire ← CoreCreate.CreateWire[coreDesign, SCTestA, "nandInst22W"];
nandInst23W: Core.Wire ← CoreCreate.CreateWire[coreDesign, SCTestA, "nandInst23W"];
nandInst24W: Core.Wire ← CoreCreate.CreateWire[coreDesign, SCTestA, "nandInst24W"];
nandInst31W: Core.Wire ← CoreCreate.CreateWire[coreDesign, SCTestA, "nandInst31W"];
nandInst32W: Core.Wire ← CoreCreate.CreateWire[coreDesign, SCTestA, "nandInst32W"];
nandInst33W: Core.Wire ← CoreCreate.CreateWire[coreDesign, SCTestA, "nandInst33W"];
nandInst34W: Core.Wire ← CoreCreate.CreateWire[coreDesign, SCTestA, "nandInst34W"];
nandInst41W: Core.Wire ← CoreCreate.CreateWire[coreDesign, SCTestA, "nandInst41W"];
nandInst42W: Core.Wire ← CoreCreate.CreateWire[coreDesign, SCTestA, "nandInst42W"];
nandInst43W: Core.Wire ← CoreCreate.CreateWire[coreDesign, SCTestA, "nandInst43W"];
nandInst44W: Core.Wire ← CoreCreate.CreateWire[coreDesign, SCTestA, "nandInst44W"];
nandInst51W: Core.Wire ← CoreCreate.CreateWire[coreDesign, SCTestA, "nandInst51W"];
nandInst52W: Core.Wire ← CoreCreate.CreateWire[coreDesign, SCTestA, "nandInst52W"];
nandInst53W: Core.Wire ← CoreCreate.CreateWire[coreDesign, SCTestA, "nandInst53W"];
nandInst54W: Core.Wire ← CoreCreate.CreateWire[coreDesign, SCTestA, "nandInst54W"];
nandInst11: CoreClasses.CellInstance ← CoreCreate.CreateCellInstance[coreDesign, SCTestA, nand, "InA: Col1, InB: Row1, Out: nandInst11W", NIL, "nandInst11"];
nandInst12: CoreClasses.CellInstance ← CoreCreate.CreateCellInstance[coreDesign, SCTestA, nand, "InA: Col2, InB: nandInst11W, Out: nandInst12W", NIL, "nandInst12"];
nandInst13: CoreClasses.CellInstance ← CoreCreate.CreateCellInstance[coreDesign, SCTestA, nand, "InA: Col3, InB: nandInst12W, Out: nandInst13W", NIL, "nandInst13"];
nandInst14: CoreClasses.CellInstance ← CoreCreate.CreateCellInstance[coreDesign, SCTestA, nand, "InA: Col4, InB: nandInst13W, Out: nandInst14W", NIL, "nandInst14"];
nandInst15: CoreClasses.CellInstance ← CoreCreate.CreateCellInstance[coreDesign, SCTestA, nand, "InA: Col5, InB: nandInst14W, Out: nandInst15W", NIL, "nandInst15"];
nandInst21: CoreClasses.CellInstance ← CoreCreate.CreateCellInstance[coreDesign, SCTestA, nand, "InA: Col1, InB: Row2, Out: nandInst21W", NIL, "nandInst21"];
nandInst22: CoreClasses.CellInstance ← CoreCreate.CreateCellInstance[coreDesign, SCTestA, nand, "InA: Col2, InB: nandInst11W, Out: nandInst22W", NIL, "nandInst22"];
nandInst23: CoreClasses.CellInstance ← CoreCreate.CreateCellInstance[coreDesign, SCTestA, nand, "InA: Col3, InB: nandInst12W, Out: nandInst23W", NIL, "nandInst23"];
nandInst24: CoreClasses.CellInstance ← CoreCreate.CreateCellInstance[coreDesign, SCTestA, nand, "InA: Col4, InB: nandInst13W, Out: nandInst24W", NIL, "nandInst24"];
nandInst25: CoreClasses.CellInstance ← CoreCreate.CreateCellInstance[coreDesign, SCTestA, nand, "InA: Col5, InB: nandInst14W, Out: nandInst25W", NIL, "nandInst25"];
nandInst31: CoreClasses.CellInstance ← CoreCreate.CreateCellInstance[coreDesign, SCTestA, nand, "InA: Col1, InB: Row3, Out: nandInst31W", NIL, "nandInst31"];
nandInst32: CoreClasses.CellInstance ← CoreCreate.CreateCellInstance[coreDesign, SCTestA, nand, "InA: Col2, InB: nandInst11W, Out: nandInst32W", NIL, "nandInst32"];
nandInst33: CoreClasses.CellInstance ← CoreCreate.CreateCellInstance[coreDesign, SCTestA, nand, "InA: Col3, InB: nandInst12W, Out: nandInst33W", NIL, "nandInst33"];
nandInst34: CoreClasses.CellInstance ← CoreCreate.CreateCellInstance[coreDesign, SCTestA, nand, "InA: Col4, InB: nandInst13W, Out: nandInst34W", NIL, "nandInst34"];
nandInst35: CoreClasses.CellInstance ← CoreCreate.CreateCellInstance[coreDesign, SCTestA, nand, "InA: Col5, InB: nandInst14W, Out: nandInst35W", NIL, "nandInst35"];
nandInst41: CoreClasses.CellInstance ← CoreCreate.CreateCellInstance[coreDesign, SCTestA, nand, "InA: Col1, InB: Row4, Out: nandInst41W", NIL, "nandInst41"];
nandInst42: CoreClasses.CellInstance ← CoreCreate.CreateCellInstance[coreDesign, SCTestA, nand, "InA: Col2, InB: nandInst11W, Out: nandInst42W", NIL, "nandInst42"];
nandInst43: CoreClasses.CellInstance ← CoreCreate.CreateCellInstance[coreDesign, SCTestA, nand, "InA: Col3, InB: nandInst12W, Out: nandInst43W", NIL, "nandInst43"];
nandInst44: CoreClasses.CellInstance ← CoreCreate.CreateCellInstance[coreDesign, SCTestA, nand, "InA: Col4, InB: nandInst13W, Out: nandInst44W", NIL, "nandInst44"];
nandInst45: CoreClasses.CellInstance ← CoreCreate.CreateCellInstance[coreDesign, SCTestA, nand, "InA: Col5, InB: nandInst14W, Out: nandInst45W", NIL, "nandIns45"];
nandInst51: CoreClasses.CellInstance ← CoreCreate.CreateCellInstance[coreDesign, SCTestA, nand, "InA: Col1, InB: Row5, Out: nandInst51W", NIL, "nandInst51"];
nandInst52: CoreClasses.CellInstance ← CoreCreate.CreateCellInstance[coreDesign, SCTestA, nand, "InA: Col2, InB: nandInst11W, Out: nandInst52W", NIL, "nandInst52"];
nandInst53: CoreClasses.CellInstance ← CoreCreate.CreateCellInstance[coreDesign, SCTestA, nand, "InA: Col3, InB: nandInst12W, Out: nandInst53W", NIL, "nandInst53"];
nandInst54: CoreClasses.CellInstance ← CoreCreate.CreateCellInstance[coreDesign, SCTestA, nand, "InA: Col4, InB: nandInst13W, Out: nandInst54W", NIL, "nandInst54"];
nandInst55: CoreClasses.CellInstance ← CoreCreate.CreateCellInstance[coreDesign, SCTestA, nand, "InA: Col5, InB: nandInst14W, Out: nandInst55W", NIL, "nandIns55"];
RETURN [coreDesign, SCTestA];
END;
DoLayout: PROC [coreDesign: Core.Design, cellType: Core.CellType, cdDesign, libDesign: CD.Design] RETURNS [result: SC.Result ← NIL] =
Create a standard cell object
BEGIN
technology: CD.Technology ← CD.FetchTechnology[$cmos];
metal: SC.Layer ← CD.FetchLayer[technology, $met];
metal2: SC.Layer ← CD.FetchLayer[technology, $met2];
rules: SC.DesignRules ← SC.CreateDesignRules[$cmos, metal, metal2, horizontal];
IF libDesign # NIL THEN
{handle: SC.Handle ← SC.CreateHandle[coreDesign, cellType, cdDesign, libDesign, rules];
SC.InitialPlace[handle];
SC.PlaceImprove[handle, $globalRouting];
SC.GlobalRoute[handle];
SC.PlaceImprove[handle, $globalRouting];
result ← SC.DetailRoute[handle]};
END;
WriteLayout: PROC [result: SC.Result, design: CD.Design] =
Write a standard cell object to a CND design
BEGIN
IF CDIO.WriteDesign[design, result.handle.name] THEN
BEGIN
newCellName: Rope.ROPE ← CDDirectory.Name[result.object];
IF ~Rope.Equal[result.handle.name, newCellName] THEN
TerminalIO.WriteRope[Rope.Cat["cell name changed to: ", newCellName, "\n"]];
END
ELSE
TerminalIO.WriteRope["Error: design not written\n"];
END;
debug: BOOLEAN ← FALSE;
coreDesign: Core.Design;
cellType: Core.CellType;
result: SC.Result;
technology: CD.Technology ← CD.FetchTechnology[$cmos];
cdDesign: CD.Design ← CDOps.CreateDesign[technology];
libName: Rope.ROPE ←"/indigo/autolayout/arbiter/StandardCells/ArbiterPartsNewPins.dale";
libDesign: CD.Design ← CDGenerateRemote.FetchRemoteDesign[cdDesign, libName];
IF libDesign = NIL THEN
{libDesign ← CDIO.ReadDesign[libName];
IF libDesign = NIL THEN
{TerminalIO.WriteRope[Rope.Cat["Unable to read Chipndale library from: ", libName, "\n"]]}
ELSE
CDGenerateRemote.CacheRemoteDesign[cdDesign, libDesign]};
[coreDesign, cellType] ← CreateCore[];
IF debug THEN {
out: IO.STREAM ← ViewerIO.CreateViewerStreams[
name: "Core: SCTestA",
viewer: NIL,
editedStream: FALSE].out;
CoreOps.PrintDesign[coreDesign, out]};
result ← DoLayout[coreDesign, cellType, cdDesign, libDesign];
WriteLayout[result, cdDesign];
END.