[Cyan]<DATools6.0>StdCell>SCTest.mesa!7

SCTest.mesa

Last Edited by: Preas, September 5, 1985 10:39:21 am PDT

Frank Bowers November 19, 1985 11:05:53 am PST

Bryan Preas September 5, 1985 10:37:21 am PDT

To run the standard cell test package:

bringover /DATools/DATools6.0/Top/StdCell21.df

sc.load

run sctest

cdread sctest

DIRECTORY

CD,

CDDirectory,

CDGenerate,

CDGenerateRemote,

CDIO,

CDOps,

Core,

CoreClasses,

CoreCompose,

CoreProperties,

IO,

Rope,

SC,

TerminalIO,

ViewerIO;

SCTest: CEDAR PROGRAM

IMPORTS CD, CDDirectory, CDGenerateRemote, CDIO, CDOps, CoreClasses, CoreCompose, CoreProperties, Rope, SC, TerminalIO, ViewerIO

SHARES SC =

BEGIN

debug: BOOLEAN ← FALSE;

TestType: TYPE = {none, tiny, small};

CreateInstance: PROC [context: CoreCompose.Context, actual: Rope.ROPE, type: Core.CellType, name: Rope.ROPE] RETURNS [instance: CoreClasses.CellInstance] = {

create a cell instance rec

instance ← NEW[CoreClasses.CellInstanceRec ← [CoreCompose.CreateWires[context, actual], type, NIL]];

CoreProperties.PutCellInstanceProp[instance, CoreClasses.instanceNameProp, name]};

CreateRecordCell: PROC [context: CoreCompose.Context, name: Rope.ROPE, public: Core.WireSequence, onlyInternal: Core.WireSequence ← NIL, instances: CoreClasses.CellInstanceList ← NIL] RETURNS [cellType: Core.CellType] = {

create a cell instance rec

internal: Core.WireSequence ← WireUnion[public, onlyInternal];

recCell: CoreClasses.RecordCellType ← NEW [CoreClasses.RecordCellTypeRec ← [

internal: internal,

instances: instances]];

cellType ← NEW [Core.CellTypeRec ← [

public: public,

data: recCell]];

};

w1.elements#NIL and w2.elements#NIL

WireUnion: PROC [w1, w2: Core.WireSequence] RETURNS [union: Core.WireSequence] = {

IF w1=NIL THEN RETURN [w2];

IF w2=NIL THEN RETURN [w1];

union ← NEW [Core.WireSequenceRec[w1.size+w2.size]];

FOR i: INT IN [0..w1.size) DO union[i] ← w1[i] ENDLOOP;

FOR i: INT IN [0..w2.size) DO union[i+w1.size] ← w2[i] ENDLOOP;

};

CreateCoreTiny: PROC [] RETURNS [CoreCompose.Context, Core.CellType] =

Create a Core design

BEGIN

context: CoreCompose.Context ← CoreCompose.CreateContext[];

nandWires: CoreCompose.WireSequence ← CoreCompose.CreateWires[context, "InA, InB, Out"];

nand: Core.CellType ← CreateRecordCell[context, "NAND", nandWires, NIL, NIL];

invWires: CoreCompose.WireSequence ← CoreCompose.CreateWires[context, "In, Out"];

inverter: Core.CellType ← CreateRecordCell[context, "Inverter", invWires, NIL, NIL];

nandInst: CoreClasses.CellInstance ← CreateInstance[context, "InA, InB, NOut", nand, "nandInst"];

invInst: CoreClasses.CellInstance ← CreateInstance[context, "NOut, Out", inverter, "invInst"];

pubWires: CoreCompose.WireSequence ← CoreCompose.CreateWires[context, "InA, InB, Out"];

privWires: CoreCompose.WireSequence ← CoreCompose.CreateWires[context, "NOut"];

SCTest: Core.CellType ← CreateRecordCell[context, "SCTest", pubWires, privWires, LIST[nandInst, invInst]];

IF debug THEN {

out: IO.STREAM ← ViewerIO.CreateViewerStreams[

viewer: NIL,

editedStream: FALSE].out;

CoreClasses.RecordPrint[NARROW[SCTest.data], out]};

RETURN [context, SCTest];

END;

CreateCoreSmall: PROC [] RETURNS [CoreCompose.Context, Core.CellType] =

Create a Core design

BEGIN

context: CoreCompose.Context ← CoreCompose.CreateContext[];

nandWires: CoreCompose.WireSequence ← CoreCompose.CreateWires[context, "InA, InB, Out"];

nand: Core.CellType ← CreateRecordCell[context, "NAND", nandWires, NIL, NIL];

nandInst11: CoreClasses.CellInstance ← CreateInstance[context, "Col1, Row1, nandInst11W", nand, "nandInst11"];

nandInst12: CoreClasses.CellInstance ← CreateInstance[context, "Col2, nandInst11W, nandInst12W", nand, "nandInst12"];

nandInst13: CoreClasses.CellInstance ← CreateInstance[context, "Col3, nandInst12W, nandInst13W", nand, "nandInst13"];

nandInst14: CoreClasses.CellInstance ← CreateInstance[context, "Col4, nandInst13W, nandInst14W", nand, "nandInst14"];

nandInst15: CoreClasses.CellInstance ← CreateInstance[context, "Col5, nandInst14W, nandInst15W", nand, "nandInst15"];

nandInst21: CoreClasses.CellInstance ← CreateInstance[context, "Col1, Row2, nandInst21W", nand, "nandInst21"];

nandInst22: CoreClasses.CellInstance ← CreateInstance[context, "Col2, nandInst21W, nandInst22W", nand, "nandInst22"];

nandInst23: CoreClasses.CellInstance ← CreateInstance[context, "Col3, nandInst22W, nandInst23W", nand, "nandInst23"];

nandInst24: CoreClasses.CellInstance ← CreateInstance[context, "Col4, nandInst23W, nandInst24W", nand, "nandInst24"];

nandInst25: CoreClasses.CellInstance ← CreateInstance[context, "Col5, nandInst24W, nandInst25W", nand, "nandInst25"];

nandInst31: CoreClasses.CellInstance ← CreateInstance[context, "Col1, Row3, nandInst31W", nand, "nandInst31"];

nandInst32: CoreClasses.CellInstance ← CreateInstance[context, "Col2, nandInst31W, nandInst32W", nand, "nandInst32"];

nandInst33: CoreClasses.CellInstance ← CreateInstance[context, "Col3, nandInst32W, nandInst33W", nand, "nandInst33"];

nandInst34: CoreClasses.CellInstance ← CreateInstance[context, "Col4, nandInst33W, nandInst34W", nand, "nandInst34"];

nandInst35: CoreClasses.CellInstance ← CreateInstance[context, "Col5, nandInst34W, nandInst35W", nand, "nandInst35"];

nandInst41: CoreClasses.CellInstance ← CreateInstance[context, "Col1, Row4, nandInst41W", nand, "nandInst41"];

nandInst42: CoreClasses.CellInstance ← CreateInstance[context, "Col2, nandInst41W, nandInst42W", nand, "nandInst42"];

nandInst43: CoreClasses.CellInstance ← CreateInstance[context, "Col3, nandInst42W, nandInst43W", nand, "nandInst43"];

nandInst44: CoreClasses.CellInstance ← CreateInstance[context, "Col4, nandInst43W, nandInst44W", nand, "nandInst44"];

nandInst45: CoreClasses.CellInstance ← CreateInstance[context, "Col5, nandInst44W, nandInst45W", nand, "nandInst45"];

nandInst51: CoreClasses.CellInstance ← CreateInstance[context, "Col1, Row5, nandInst51W", nand, "nandInst51"];

nandInst52: CoreClasses.CellInstance ← CreateInstance[context, "Col2, nandInst51W, nandInst52W", nand, "nandInst52"];

nandInst53: CoreClasses.CellInstance ← CreateInstance[context, "Col3, nandInst52W, nandInst53W", nand, "nandInst53"];

nandInst54: CoreClasses.CellInstance ← CreateInstance[context, "Col4, nandInst53W, nandInst54W", nand, "nandInst54"];

nandInst55: CoreClasses.CellInstance ← CreateInstance[context, "Col5, nandInst54W, nandInst55W", nand, "nandInst55"];

pubWires: CoreCompose.WireSequence ← CoreCompose.CreateWires[context, "Row1, Row2, Row3, Row4, Row5, Col1, Col2, Col3, Col4, Col5, nandInst15W, nandInst25W, nandInst35W, nandInst45W, nandInst55W"];

privWires: CoreCompose.WireSequence ← CoreCompose.CreateWires[context, "nandInst11W, nandInst12W, nandInst13W, nandInst14W, nandInst21W, nandInst22W, nandInst23W, nandInst24W, nandInst31W, nandInst32W, nandInst33W, nandInst34W, nandInst41W, nandInst42W, nandInst43W, nandInst44W, nandInst51W, nandInst52W, nandInst53W, nandInst54W"];

SCTest: Core.CellType ← CreateRecordCell[context, "SCTest", pubWires, privWires, LIST[nandInst11, nandInst12, nandInst13, nandInst14, nandInst15, nandInst21, nandInst22, nandInst23, nandInst24, nandInst25, nandInst31, nandInst32, nandInst33, nandInst34, nandInst35, nandInst41, nandInst42, nandInst43, nandInst44, nandInst45, nandInst51, nandInst52, nandInst53, nandInst54, nandInst55]];

IF debug THEN {

out: IO.STREAM ← ViewerIO.CreateViewerStreams[

viewer: NIL,

editedStream: FALSE].out;

CoreClasses.RecordPrint[NARROW[SCTest.data], out]};

RETURN [context, SCTest];

END;

DoLayout: PROC [context: CoreCompose.Context, cellType: Core.CellType, cdDesign, libDesign: CD.Design] RETURNS [result: SC.Result ← NIL] =

Create a standard cell object

BEGIN

technology: CD.Technology ← CD.FetchTechnology[$cmos];

metal: SC.Layer ← CD.FetchLayer[technology, $met];

metal2: SC.Layer ← CD.FetchLayer[technology, $met2];

rules: SC.DesignRules ← SC.CreateDesignRules[$cmos, metal, metal2, horizontal];

IF libDesign # NIL THEN

{handle: SC.Handle ← SC.CreateHandle[context, cellType, cdDesign, libDesign, rules, "SCTest"];

SC.InitialPlace[handle];

SC.GlobalRoute[handle];

SC.PlaceImprove[handle, $globalRouting];

result ← SC.DetailRoute[handle]};

END;

WriteLayout: PROC [result: SC.Result, design: CD.Design] =

Write a standard cell object to a CND design

BEGIN

IF CDIO.WriteDesign[design, result.handle.name] THEN

BEGIN

newCellName: Rope.ROPE ← CDDirectory.Name[result.object];

IF ~Rope.Equal[result.handle.name, newCellName] THEN

TerminalIO.WriteRope[Rope.Cat["cell name changed to: ", newCellName, "\n"]];

END

ELSE

TerminalIO.WriteRope["Error: design not written\n"];

END;

GetTest: PROC [] RETURNS [answer: TestType ← none] =

Get test type to run

BEGIN

WHILE answer = none DO

testAnswer: Rope.ROPE ← TerminalIO.RequestRope["Enter test case size: None, Tiny or Small "];

SELECT TRUE FROM

Rope.Equal[testAnswer, "Tiny"] => answer ← tiny;

Rope.Equal[testAnswer, "Small"] => answer ← small;

Rope.Equal[testAnswer, "None"] => EXIT;

ENDCASE;

ENDLOOP;

END;

context: CoreCompose.Context;

cellType: Core.CellType;

result: SC.Result;

technology: CD.Technology ← CD.FetchTechnology[$cmos];

cdDesign: CD.Design ← CDOps.CreateDesign[technology];

answer: TestType ← GetTest[];

libName: Rope.ROPE ←"ArbiterParts.dale";

libDesign: CD.Design ← CDGenerateRemote.FetchRemoteDesign[cdDesign, libName];

IF libDesign = NIL THEN

{libDesign ← CDIO.ReadDesign[libName];

IF libDesign = NIL THEN

{TerminalIO.WriteRope[Rope.Cat["Unable to read Chipndale library from: ", libName, "\n"]]}

ELSE

CDGenerateRemote.CacheRemoteDesign[cdDesign, libDesign]};

SELECT answer FROM

tiny => [context, cellType] ← CreateCoreTiny[];

small => [context, cellType] ← CreateCoreSmall[];

ENDCASE;

IF answer # none THEN {

result ← DoLayout[context, cellType, cdDesign, libDesign];

WriteLayout[result, cdDesign]};

END.