SCImpl:
CEDAR
PROGRAM
IMPORTS CD, CDCells, CDDirectory, CDGenerateRemote, Rope, Route, RTBasic, SC, SCChanUtil, SCInitialPlace, SCInstUtil, SCPlaceUtil, SCPrivate, SCRowUtil, SCSmash, SCWidthUtil, SCUtil, TerminalIO
EXPORTS SC
SHARES SC = {
debug: BOOLEAN ← FALSE;
Error: PUBLIC ERROR[errorType: SC.ErrorType ← callingError, explanation: Rope.ROPE ← NIL] = CODE;
Signal: PUBLIC SIGNAL[signalType: SC.ErrorType ← callingError, explanation: Rope.ROPE ← NIL] = CODE;
CreateDesignRules:
PUBLIC
PROC [technologyKey:
ATOM, horizLayer, vertLayer:
SC.Layer, rowDirection:
SC.Direction, properties:
SC.Properties ←
NIL]
RETURNS [designRules:
SC.DesignRules] =
Define the standard cell design rules. technologyKey values are predefinded for now.
BEGIN
designRules ← NEW[SC.DesignRulesRec];
designRules.technology ← CD.FetchTechnology[technologyKey];
designRules.rowRules ← Route.CreateDesignRules[technologyKey, horizLayer, vertLayer, rowDirection, properties];
designRules.sideRules ← Route.CreateDesignRules[technologyKey, horizLayer, vertLayer, RTBasic.OtherDirection[rowDirection], properties];
END;
CreateHandle:
PUBLIC
PROC [coreContext: CoreCompose.Context, cellType: Core.CellType, cdDesign, libDesign:
CD.Design, designRules:
SC.DesignRules, name: Rope.
ROPE ←
NIL, properties:
SC.Properties ←
NIL]
RETURNS [handle:
SC.Handle] =
Create a standard cell design. The standard cell design definition includes the design rules (conductor and via widths and spacings) and the circuit definition.
BEGIN
parms: SCPrivate.Parms ← NARROW[NEW[SCPrivate.ParmsRec], SCPrivate.Parms];
IF designRules = NIL THEN SC.Error[callingError, "No design rules."];
IF coreContext = NIL THEN SC.Error[callingError, "No Core context."];
IF libDesign = NIL THEN SC.Error[callingError, "No ChipNDale design."];
handle ← NEW[SC.HandleRec];
handle.name ← name;
handle.rules ← designRules;
handle.properties ← properties;
handle.coreContext ← coreContext;
parms.libDesign ← libDesign;
parms.cdDesign ← cdDesign;
parms.cdTable ← CDGenerateRemote.GetRemoteTable[libDesign.name];
handle.parms ← parms;
set up the layout data
IF ~SCPrivate.SetUpLayout[handle] THEN RETURN[NIL];
set up the structure data
IF ~SCPrivate.GetStructure[handle, cellType] THEN RETURN[NIL];
END;
InitialPlace:
PUBLIC
PROC [handle:
SC.Handle] = {
Determine an initial placement for the instances.
layoutData: SCPrivate.LayoutData ← NARROW[handle.layoutData];
SCSmash.RemoveSmash[handle];
SCPlaceUtil.ClrCurPlac[handle, TRUE];
SCChanUtil.InitChanWidths[handle];
SCInitialPlace.PrePlace[handle, TRUE];
SCInitialPlace.RowInit[handle];
SCInitialPlace.PosInit[handle];
[layoutData.lgRows.maxRowWidth, layoutData.lgRows.numMaxRows] ← SCRowUtil.FindMaxRow[handle];
SCWidthUtil.AllChanWidths[handle, areaFom];
SCInstUtil.AsgnChanPos[handle];
IF debug THEN SCPlaceUtil.WriteCurPlace[handle];
[] ← SCUtil.WriteResults["End initial placement\n initial size:", handle, 0]};
PlaceImprove:
PUBLIC
PROC [handle:
SC.Handle, algorithm:
ATOM] = {
Improve the placement for the instances. Available algorithms consist of the following: $simulatedAnealing, $pairWiseImprovement
SELECT algorithm
FROM
$simulatedAnealing =>NULL;
$pairWiseImprovement =>NULL;
$globalRouting => SCPrivate.PosImprove[handle, areaFom];
ENDCASE};
GlobalRoute:
PUBLIC
PROC [handle:
SC.Handle] = {
Determine strategic paths for the wiring that must cross cell rows.
SCSmash.RemoveSmash[handle];
SCSmash.SmashAllNets[handle, TRUE]};
DetailRoute:
PUBLIC
PROC [handle:
SC.Handle]
RETURNS [result:
SC.Result] =
Determine actual wiring paths.
BEGIN
parms: SCPrivate.Parms ← NARROW[handle.parms];
result ← SCPrivate.DetailRoute[handle];
IF parms.cdDesign #
NIL
THEN
{application: CD.Instance;
IF ~ CDDirectory.Include[parms.cdDesign, result.object, handle.name]
THEN
TerminalIO.WriteRope[Rope.Cat[" unable to add channel: ", handle.name, " in design"]];
CDCells.SetInterestRect[result.object, result.rect];
[] ← CDCells.RepositionCell[result.object, parms.cdDesign];
[application, ] ← CDCells.IncludeOb[design: parms.cdDesign, cell: NIL, ob: result.object, cellCSystem: originCoords, obCSystem: originCoords]};
END;
CreateLayout:
PUBLIC
PROC [technologyKey:
ATOM, horizLayer, vertLayer:
SC.Layer, rowDirection:
SC.Direction, coreContext: CoreCompose.Context, cellType: Core.CellType, cdDesign, libDesign:
CD.Design ←
NIL, name: Rope.
ROPE ←
NIL, properties:
SC.Properties ←
NIL]
RETURNS [object:
CD.Object] = {
Create a standard cell object by performing the above operations
result: SC.Result;
designRules: SC.DesignRules ← SC.CreateDesignRules[technologyKey, horizLayer, vertLayer, rowDirection, properties];
handle: SC.Handle ← SC.CreateHandle[coreContext, cellType, cdDesign, libDesign, designRules, name, properties];
SC.InitialPlace[handle];
SC.PlaceImprove[handle, $pairWiseImprovement];
SC.GlobalRoute[handle];
result ← SC.DetailRoute[handle];
RETURN [result.object];
};
}.