[Cyan]<DATools6.0>StdCell>SC.mesa!3

SC.mesa ///StdCell/SC.mesa

Last Edited by: Preas, November 7, 1985 10:11:48 am PST

DIRECTORY

CD,

Core,

CoreCompose,

D2Basic,

List,

Rope,

Route,

RTBasic;

SC: CEDAR DEFINITIONS = BEGIN

Theory

This interface defines the basic data structures and procedures to define a standard cell object from a Core description.

Common Types

RopeList: TYPE = LIST OF Rope.ROPE;

Layer: TYPE = CD.Layer;

Rect: TYPE = D2Basic.Rect;

RefRect: TYPE = REF Rect;

Pos: TYPE = D2Basic.Pos;

Number: TYPE = D2Basic.Number;

SideOrNone: TYPE = RTBasic.SideOrNone;

Side: TYPE = RTBasic.Side;

DirectionOrNone: TYPE = RTBasic.DirectionOrNone;

Direction: TYPE = RTBasic.Direction;

Properties: TYPE = List.AList;

Errors

Error: ERROR [errorType: ErrorType ← callingError, explanation: Rope.ROPE ← NIL];

Signal: SIGNAL [signalType: ErrorType ← callingError, explanation: Rope.ROPE ← NIL];

ErrorType: TYPE = {programmingError, callingError, noResource, other};

Design Rules

DesignRules: TYPE = REF DesignRulesRec;

DesignRulesRec: TYPE = RECORD[

rowRules, sideRules: Route.DesignRules,

technology: PRIVATE REF ANY ← NIL,

properties: Properties ← NIL];

CreateDesignRules: PROC [technologyKey: ATOM, horizLayer, vertLayer: Layer, rowDirection: Direction, properties: Properties ← NIL] RETURNS [designRules: DesignRules];

Define the standard cell design rules. technologyKey values must correspond to one of the ChipNDale technologies.

StdCell Design

Handle: TYPE = REF HandleRec;

HandleRec: TYPE = RECORD [

name: Rope.ROPE ← NIL,

coreContext: CoreCompose.Context ← NIL,

rules: DesignRules ← NIL,

properties: Properties ← NIL,

parms: PRIVATE REF ANY ← NIL,

structureData: PRIVATE REF ANY ← NIL,

layoutData: PRIVATE REF ANY ← NIL];

Result: TYPE = REF ResultRec;

ResultRec: TYPE = RECORD[

handle: Handle,

object: CD.Object,

rect: Rect ← [0, 0, 0, 0],

polyLength, metalLength, metal2Length, polyToMetal, metalToMetal2: NAT ← 0,

numIncompletes: NAT ← 0,

incompleteNets: RopeList ← NIL];

CreateHandle: PROC [coreContext: CoreCompose.Context, cellType: Core.CellType, cdDesign, libDesign: CD.Design, designRules: DesignRules, name: Rope.ROPE ← NIL, properties: Properties ← NIL] RETURNS [handle: Handle];

Create a StdCellHandle. The StdCellHandle definition includes the design rules (conductor and via widths and spacings) for the routing channels as well as the circuit structure definition.

Standard Cell Optimization and Construction

The following operations are available for a standard cell design.

InitialPlace: PROC [handle: Handle];

Determine an initial placement for the instances.

PlaceImprove: PROC [handle: Handle, algorithm: ATOM];

Improve the placement for the instances. Available algorithms consist of the following: $simulatedAnealing, pairWiseImprovement

GlobalRoute: PROC [handle: Handle];

Determine strategic paths for the wiring that must cross cell rows.

DetailRoute: PROC [handle: Handle] RETURNS [result: Result];

Determine actual wiring paths. Create a ChipNDale object and include the placement and routing in the object. This object will be included in design if design # NIL (form CreateHandle).

Sugar

CreateLayout: PROC [technologyKey: ATOM, horizLayer, vertLayer: Layer, rowDirection: Direction, coreContext: CoreCompose.Context, cellType: Core.CellType, cdDesign, libDesign: CD.Design ← NIL, name: Rope.ROPE ← NIL, properties: Properties ← NIL] RETURNS [object: CD.Object];

Create a standard cell object by performing the above operations

END.