DIRECTORY CD USING [combined, CreateDrawRef, DrawRectProc, DrawRef, Instance, Layer], CDBasics USING [Intersection, NonEmpty, ToRect], CDInstances USING [NewInstance], CDOps USING [LayerName], CDOrient USING [original, MapRect], CDPinObjects USING [EnumeratePins, GetLayer, GetName, GetOwner, InstanceEnumerator], IO USING [Close, EndOf, Error, RIS, SkipWhitespace, STREAM], Properties USING [GetProp, PutProp], Rope USING [Cat, Equal, ROPE], SX USING [AddRect, AdjustNode, Circuit, CircuitNode, IllegalLayer, LogicalCell, SignalName, SpinifexLayerIndex], SXAccess, SXAccessInternal, SXAtoms USING [SignalName, spinifexCircuitDescription], SXUserExtract, SymTab USING [Create, Fetch, Ref, Store]; SXUserExtractImpl: CEDAR PROGRAM IMPORTS CD, CDBasics, CDInstances, CDOps, CDOrient, CDPinObjects, IO, Properties, Rope, SX, SXAccess, SXAccessInternal, SXAtoms, SymTab EXPORTS SXUserExtract = BEGIN ConnectionPin: PROCEDURE [app: CD.Instance] RETURNS [BOOLEAN] ~ { RETURN [CDPinObjects.GetOwner[app] = NIL AND CDPinObjects.GetLayer[app] # CD.combined] }; DataForRects: TYPE ~ RECORD [ pinLayer: CD.Layer, pinName: Rope.ROPE, cir: REF SX.Circuit, ports: SymTab.Ref ]; TranslateCell: PUBLIC PROCEDURE [cell: REF SX.LogicalCell, CircuitDescription: Rope.ROPE] ~ { AddPinRects: CDPinObjects.InstanceEnumerator ~ { IF ConnectionPin[inst] THEN { dataRef: REF DataForRects _ NEW[DataForRects]; dr: CD.DrawRef ~ CD.CreateDrawRef[NIL]; fakeAppl: CD.Instance = CDInstances.NewInstance[ob~ cell.cellObj]; fakeAppl.location _ [0, 0]; dr.drawRect _ CaptureGeomInPin; dr.devicePrivate _ dataRef; dr.stopFlag _ SXAccess.stopFlag; dr.interestClip _ CDOrient.MapRect[itemInCell~ CDBasics.ToRect[[0,0], inst.ob.size], cellSize~ inst.ob.size, cellInstOrient~ inst.orientation, cellInstPos~ inst.location]; dataRef.pinLayer _ CDPinObjects.GetLayer[inst]; dataRef.pinName _ CDPinObjects.GetName[inst]; dataRef.cir _ cell.circuit; dataRef.ports _ ports; cell.cellObj.class.drawMe[fakeAppl, [0, 0], CDOrient.original, dr ! SX.IllegalLayer => { SXAccessInternal.PutError[ob: cell.cellObj, r: dr.interestClip, message: Rope.Cat["Material on level ", CDOps.LayerName[dataRef.pinLayer], " may not appear as an isolated rectangle.\n"]]; GOTO BadRect } ]; EXITS BadRect => NULL }; quit _ FALSE }; -- end AddPinRects ports: SymTab.Ref ~ SymTab.Create[521]; cell.circuit.properties _ Properties.PutProp [cell.circuit.properties, SXAtoms.spinifexCircuitDescription, SXAtoms.spinifexCircuitDescription]; IF ~ Rope.Equal [CircuitDescription, "()"] THEN { [] _ CDPinObjects.EnumeratePins[cell.cellObj, AddPinRects]; ReadPortOrder[ cell, IO.RIS[CircuitDescription], ports]; }; }; CaptureGeomInPin: CD.DrawRectProc -- [r: DesignRect, l: Layer, pr: DrawRef] -- ~ { data: REF DataForRects ~ NARROW[pr.devicePrivate]; IF l = data.pinLayer THEN { r _ CDBasics.Intersection[r, pr.interestClip]; IF CDBasics.NonEmpty[r] THEN { node: REF SX.CircuitNode ~ SX.AddRect[ cir~ data.cir, lev~ l, dim~ r, value~ NARROW[data.ports.Fetch[data.pinName].val]]; IF node # NIL THEN { Layers: TYPE ~ SX.SpinifexLayerIndex; [] _ data.ports.Store[data.pinName, node]; FOR layer: Layers IN [Layers.FIRST .. SXAccess.sxTech.numSpinifexLayers) DO SX.AdjustNode[node, layer, 0, 0, absolute]; ENDLOOP; IF Properties.GetProp [node.properties, SXAtoms.SignalName] = NIL THEN node.properties _ Properties.PutProp [node.properties, SXAtoms.SignalName, NEW[ SX.SignalName _ [name~ data.pinName]]] }; } } }; ReadPortOrder: PROC [cell: REF SX.LogicalCell, from: IO.STREAM, ports: SymTab.Ref] ~ { ENABLE IO.Error => { }; DO [] _ from.SkipWhitespace[]; IF from.EndOf[] THEN EXIT; EXIT; ENDLOOP; from.Close[]; }; END. LSXUserExtractImpl.mesa Copyright c 1984, 1985 by Xerox Corporation. All rights reserved. Written by Shand, March 7, 1985 8:41:53 pm PST Last Edited by Shand, March 13, 1985 4:42:32 am PST Last Edited by Jacobi, April 8, 1985 12:42:12 pm PST Last edited by: gbb November 6, 1985 6:24:53 pm PST -- Flag this cell for special output handling. And now do something about making node order match port order. Now do something to generate cell exclusion regions. Do bloating & shrinking cleanups on these regions and something to make sure pins are accessible. And insert the resulting boxes using AddBox. -- value parameter may be NIL node has not been added yet -- Process SpinifexCircuitDescription property (a ROPE) to determine order of Thyme ports for cell. Edited on May 6, 1985 11:26:55 am PDT, by Beretta Converted to ChipNDale CD20 Κ˜codešœ™Kšœ Οmœ7™BK™.K™3K™4K™3—unitšΟk ˜ KšžœžœC˜KKšœ žœ"˜0Kšœ žœ˜ Kšœžœ ˜Kšœ žœ˜#Kšœ žœB˜TKšžœžœžœžœ˜K˜—K™4K™1K™/K™,Kšœ˜—šŸœžœΠcs,œ˜RKšœžœžœ˜2šžœžœ˜Kšœ.˜.šžœžœ˜Kšœ:™:KšœžœDžœ&˜yšžœžœžœ˜Kšœžœ˜%Lšœ*˜*šžœžœ žœ'ž˜KKšœ+˜+Kšžœ˜—šžœ<žœž˜FKšœKžœ(˜v—Kšœ˜—K˜—K˜—K˜—š  œžœžœž œ˜VK™cšžœžœ ˜K˜—šž˜K˜Kšžœžœžœ˜Kšžœ˜Kšžœ˜—K˜ J˜—Kšž˜™1K™—K˜—…—>