TranslateGeometry: PROCEDURE [cell: REF LogicalCell];

AddBox adds a box to a particular analysis layer when fine control or asymetric interest bloating is required. The box, of dimension dim is transform according to appl.

AddRect adds a Rectangle from a normal chipndale mask level, to each of the analysis layers which the techHandle dictates. May raise ERROR IllegalLayer.

CreateLinkage: PROCEDURE [ cir: REF Circuit, source: CD.Instance, length, width: CD.Number] RETURNS [REF NodeLinkage];

LinkageAttach: PROCEDURE [link: REF NodeLinkage, attachType: ATOM, node: REF CircuitNode ← NIL];

NormalizeCircuit: PROCEDURE [cir: REF Circuit];

LookupNode: PROCEDURE [l: REF CircuitNode] RETURNS [REF CircuitNode];

FindRootNode: PROCEDURE [ -- look at HighlightNode for usage
 circuit: REF Circuit,
 subcircuitNode: REF CircuitNode,
 qualifier: LIST OF CD.Instance,
 insertIfNotInCircuit: BOOLEAN ← FALSE]
RETURNS [
 node: REF CircuitNode,
 rootQualifier: LIST OF CD.Instance];

MergeNode: PROCEDURE [circuit: REF Circuit, to, from: REF CircuitNode];

AdjustmentMode: TYPE = {relative, absolute};

AnalysisState: TYPE = {notYetDone, useCircuit, reservedForFuture};

A node is a conductive region. When nodes are merged as a result of an overlap or abutment of similar rectangles, the estimated capacitance to ground must be adjsted due to the change in perimeter and area of these regions when combined.

Circuit: TYPE = RECORD [
nodes: LIST OF REF CircuitNode ← NIL,
linkages: LIST OF REF NodeLinkage ← NIL,
linkageCount: RECORD [inSelf: INT ← 0, inChildren: INT ← 0],
subcircuits: CD.InstanceList ← NIL, -- copies; have instance names
mergeDirectory: RefTab.Ref ← NIL, -- establishes a correspondence between a node in this cell and a node in a cell at the end of a chain of cell instantations. Key: Circuit node (of a subcircuit); val: MergeRecList.
properties: Properties.PropList ← NIL,
invocationKey: INT, -- remove !!
spinifexLayers: ARRAY SpinifexLayerIndex OF SXQuadTree.QuadTreeRoot]; -- build up on 1st step: translate

CircuitNode: TYPE = RECORD [
superceded: REF CircuitNode ← NIL, -- NIL if analysis finished
dim: LIST OF AreaPerimRec ← NIL,
loc: NodeLocation,
properties: Properties.PropList ← NIL];

NodeLocation: TYPE = RECORD [xy: CD.Position, layer: SpinifexLayerIndex];

AreaPerimRec: TYPE = RECORD [layer: SpinifexLayerIndex, area, perim: INT];

SignalName: TYPE = RECORD [
depth: INTEGER ← 0,
name: Rope.ROPE,
alias: REF SignalName ← NIL,
makePort: BOOL ← FALSE]; -- in a root cell it will be considered to be a port

Constraint may contain circular REF chains, however they are a small in number fixed at compile time by the tech. dependent client software.

NodeLinkage: TYPE = RECORD [ -- transistors
source: CD.Instance,
l, w: CD.Number, -- length, width
nodes: LIST OF REF AttachedNode ← NIL];

AttachedNode: TYPE = RECORD [
attachmentType: ATOM, -- e.g. $Gate, $Drain, $Source
node: REF CircuitNode];

MergeRecList: TYPE = LIST OF MergeRec;

ConversionProc: TYPE = PROCEDURE [inst: CD.Instance, pos: CD.Position, orient: CD.Orientation, cir: REF Circuit];

BoxMapProc: TYPE = PROCEDURE [cir: REF Circuit, dim: CD.Rect, inst: CD.Instance, pos: CD.Position, orient: CD.Orientation, node: REF CircuitNode] RETURNS [cirNode: REF CircuitNode ← NIL];

maxSpinifexLayer: INTEGER = 8;

TechHandle: TYPE = RECORD [

CombineNodePropertyProc: TYPE = PROCEDURE [circuit: REF Circuit, to, from: Properties.PropList, fromNesting: LIST OF CD.Instance] RETURNS [Properties.PropList];

CellPostProcessProc: TYPE = PROCEDURE [cell: REF LogicalCell];

LayerNames: TYPE = RECORD [layerId: ATOM ← NIL, thymeName: Rope.ROPE ← NIL];

MapRec: TYPE = RECORD [
spinifexLayer: SpinifexLayerIndex,
bloatFactor: INTEGER,
value: REF ANY ← NIL];

So how does checking work? The four quads around a corner are mapped through trigger1 to TRUE/FALSE value for each quadrant. The TRUE area represents 'stuff' and if it forms a convex or concave corner a check is made of size extent into the corresponding 'non-stuff' in the FALSE region. To do a width check we map space to TRUE and the material being width checked to FALSE, thus an appropriate check is generated extending into the material. The check fails if anything in the check region maps through trigger2 to TRUE. If okIfConnected is TRUE then the violation is overidden if trigger1 and trigger2 circuit nodes and are the same.

GeometricRule: TYPE = RECORD [
extent: INTEGER,
message: Rope.ROPE ← NIL,
okIfConnected: BOOLEAN ← FALSE,
trigger1, trigger2: PACKED ARRAY ConstraintIndex OF BOOLEAN ← ALL [FALSE]];

END.