<> <> <> <> <<>> <> <> DIRECTORY CD USING [combined, Design, Instance, Layer, Number, Orientation, Position, Rect], CDBasics USING [empty], Core USING [CellType, Wire], Rope USING [ROPE], SoSTNT USING [TNT]; SoS: CEDAR DEFINITIONS ~ BEGIN <> CheckDesignRules: PUBLIC PROC [cell: Core.CellType, design: CD.Design _ NIL, abortFlag: REF BOOL _ NIL, verbose: BOOL _ FALSE, cdObjKey, cdInstKey, cdInstListKey: ATOM]; < NIL. Design rule violations are flagged in the Core cell using the property DRV (Design Rule Violation) with key DRVkey. The property DRV is put only on cells having at least one violation.>> <> <> <<- cdObjKey is used to attach the error rectangle in the ChipNDale design. cdObjKey can be any value if ChipNDale flagging is not needed.>> <<- cdInstKey is the key to retrieve location and orientation of subcells; it is mandatory and error coreInconsistent will be raised if it proves to be wrong.>> <<- cdInstListKey is the key to retrieve the geometry of the wires; it is mandatory and nothing will be verified if it is wrong.>> <> coreInconsistent: ERROR; <> DRV: TYPE = REF DesignRuleViolation; DRVkey: ATOM; DesignRuleViolation: TYPE = RECORD [count: INT _ 0, places: LIST OF ErrorRect]; ErrorRect: TYPE = RECORD [r: CD.Rect, msg: Rope.ROPE]; <> State: TYPE = REF StateRec; StateRec: TYPE = RECORD [design: CD.Design, abort: REF BOOL, nt: SoSTNT.TNT, -- neighbourhood table maxSeparation: CD.Number _ 100, globalErrorCount: CARDINAL, verbose: BOOL, wireCreationCount: CARDINAL _ 1, -- for debugging cdObjKey: ATOM, -- key of ChipNDale object cdInstKey: ATOM, -- key of ChipNDale instance cdInstListKey: ATOM]; -- key of list of ChipNDale instances FindGeometry: TYPE = PROC [self: CD.Instance] RETURNS [r: CD.Rect _ CDBasics.empty, l: CD.Layer _ CD.combined]; <> <> CellHullProc: TYPE = PROC [self: Core.CellType, state: State] RETURNS [h: CD.Rect _ CDBasics.empty]; <> <> CheckCell: TYPE = PROC [self: Core.CellType, state: State, actual: Core.Wire, loc: CD.Position, orient: CD.Orientation]; <> <> <> MaterialToCellProc: TYPE = PROC [self: Core.CellType, state: State, actual, wire: Core.Wire, father: Core.CellType, materialLoc, cellLoc: CD.Position, materialOrient, cellOrient: CD.Orientation]; <> <> CellToCellProc: TYPE = PROC [self: Core.CellType, state: State, otherCell: Core.CellType, selfActual, otherActual: Core.Wire, father: Core.CellType, selfLoc, otherLoc: CD.Position, selfOrient, otherOrient: CD.Orientation]; <> <> END.