<> <> <> <> DIRECTORY CD, CDCells, CDIO, Core, CoreClasses, CoreCreate, CoreOps, Rope, SCTestUtil, TerminalIO, SC; SCTestUtilImpl: CEDAR PROGRAM IMPORTS CDCells, CDIO, CoreClasses, CoreCreate, CoreOps, SC, TerminalIO EXPORTS SCTestUtil = BEGIN CreateInstance: PUBLIC PROC [actual: SC.RopeList, type: Core.CellType, name: Rope.ROPE, internalWires: Core.Wire, props: Core.Properties _ NIL] RETURNS [instance: CoreClasses.CellInstance] = { <> <<>> actualWire: Core.Wire _ BindWire[actual, internalWires]; instance _ CoreClasses.CreateInstance[actualWire, type, name, props]}; CreateRecordCell: PUBLIC PROC [name: Rope.ROPE, publicWires: Core.Wire, internalWires: Core.Wire _ NIL, instances: CoreClasses.CellInstances _ NIL, props: Core.Properties _ NIL] RETURNS [cellType: Core.CellType] = { <> IF publicWires = NIL THEN publicWires _ NEW[Core.WireRec[0] _ [NIL, NULL]]; <<>> <<>> cellType _ CoreClasses.CreateRecordCell[publicWires, internalWires, instances, name, props]}; CreateWire: PUBLIC PROC [ropeList: SC.RopeList] RETURNS [wire: Core.Wire] ~ { lowr: LIST OF CoreCreate.WR _ ConvertToWR[ropeList]; wire _ CoreCreate.WireList[lowr]}; AppendInstList: PUBLIC PROC [l1, l2: CoreClasses.CellInstances] RETURNS[val: CoreClasses.CellInstances] = { z: CoreClasses.CellInstances _ NIL; val _ l2; IF l1 = NIL THEN RETURN[val]; val _ CONS[l1.first, val]; z _ val; UNTIL (l1 _ l1.rest) = NIL DO z.rest _ CONS[l1.first, z.rest]; z _ z.rest; ENDLOOP; RETURN[val]; }; AppendRopeList: PUBLIC PROC [l1, l2: SC.RopeList] RETURNS[val: SC.RopeList] = { z: SC.RopeList _ NIL; val _ l2; IF l1 = NIL THEN RETURN[val]; val _ CONS[l1.first, val]; z _ val; UNTIL (l1 _ l1.rest) = NIL DO z.rest _ CONS[l1.first, z.rest]; z _ z.rest; ENDLOOP; RETURN[val]; }; WriteLayout: PUBLIC PROC [result: SC.Result, design: CD.Design] = <> <<>> BEGIN [] _ CDCells.IncludeOb[design: design, cell: NIL, ob: result.object, position: [0, 0], orientation: CD.original, cellCSystem: interrestCoords, obCSystem: interrestCoords, mode: dontPropagate]; IF ~CDIO.WriteDesign[design, result.handle.name] THEN TerminalIO.WriteRope["Error: design not written\n"]; END; DoLayout: PUBLIC PROC [cellType: Core.CellType, cdDesign, libDesign: CD.Design, hMaterial, vMaterial: Rope.ROPE] RETURNS [result: SC.Result _ NIL] = <> BEGIN rules: SC.DesignRules _ SC.CreateDesignRules[cdDesign.technology.key, hMaterial, vMaterial, horizontal]; handle: SC.Handle _ SC.CreateHandle[cellType, cdDesign, libDesign, rules, "SCTest"]; SC.InitialPlace[handle, 0]; SC.GlobalRoute[handle]; <> result _ SC.DetailRoute[handle]; END; BindWire: PROC [actual: SC.RopeList, internalWires: Core.Wire] RETURNS [actualWire: Core.Wire] = { <> reverseWireList: LIST OF CoreCreate.WR _ NIL; newWireList: LIST OF CoreCreate.WR _ NIL; FOR rl: SC.RopeList _ actual, rl.rest UNTIL rl=NIL DO r: Rope.ROPE _ rl.first; index: INT _ CoreOps.GetWireIndex[internalWires, r]; IF index < 0 THEN SC.Error[callingError, NIL]; reverseWireList _ CONS[internalWires[index], reverseWireList]; ENDLOOP; FOR rl: LIST OF CoreCreate.WR _ reverseWireList, rl.rest UNTIL rl=NIL DO newWireList _ CONS[rl.first, newWireList]; ENDLOOP; actualWire _ CoreCreate.WireList[newWireList]; }; UnionWire: PUBLIC PROC [wire1, wire2: Core.Wire, name: Rope.ROPE _ NIL, props: Core.Properties _ NIL] RETURNS [union: Core.Wire] ~ { <> RETURN [CoreOps.UnionWire[wire1, wire2]]}; ConvertToWR: PROC [list: SC.RopeList] RETURNS[wrl: LIST OF CoreCreate.WR _ NIL] = { reverseWireList: LIST OF CoreCreate.WR _ NIL; UNTIL list = NIL DO reverseWireList _ CONS[list.first, reverseWireList]; list _ list.rest; ENDLOOP; UNTIL reverseWireList = NIL DO wrl _ CONS[reverseWireList.first, wrl]; reverseWireList _ reverseWireList.rest; ENDLOOP; RETURN[wrl]; }; -- of ConvertToWR END.